base.hh (13350:247e4108a5e8) | base.hh (13352:75647326f19b) |
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1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 59 unchanged lines hidden (view full) --- 68#include "mem/cache/tags/base.hh" 69#include "mem/cache/write_queue.hh" 70#include "mem/cache/write_queue_entry.hh" 71#include "mem/mem_object.hh" 72#include "mem/packet.hh" 73#include "mem/packet_queue.hh" 74#include "mem/qport.hh" 75#include "mem/request.hh" | 1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 59 unchanged lines hidden (view full) --- 68#include "mem/cache/tags/base.hh" 69#include "mem/cache/write_queue.hh" 70#include "mem/cache/write_queue_entry.hh" 71#include "mem/mem_object.hh" 72#include "mem/packet.hh" 73#include "mem/packet_queue.hh" 74#include "mem/qport.hh" 75#include "mem/request.hh" |
76#include "params/WriteAllocator.hh" |
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76#include "sim/eventq.hh" 77#include "sim/serialize.hh" 78#include "sim/sim_exit.hh" 79#include "sim/system.hh" 80 81class BaseMasterPort; 82class BasePrefetcher; 83class BaseSlavePort; --- 240 unchanged lines hidden (view full) --- 324 BasePrefetcher *prefetcher; 325 326 /** 327 * Notify the prefetcher on every access, not just misses. 328 */ 329 const bool prefetchOnAccess; 330 331 /** | 77#include "sim/eventq.hh" 78#include "sim/serialize.hh" 79#include "sim/sim_exit.hh" 80#include "sim/system.hh" 81 82class BaseMasterPort; 83class BasePrefetcher; 84class BaseSlavePort; --- 240 unchanged lines hidden (view full) --- 325 BasePrefetcher *prefetcher; 326 327 /** 328 * Notify the prefetcher on every access, not just misses. 329 */ 330 const bool prefetchOnAccess; 331 332 /** |
333 * The writeAllocator drive optimizations for streaming writes. 334 * It first determines whether a WriteReq MSHR should be delayed, 335 * thus ensuring that we wait longer in cases when we are write 336 * coalescing and allowing all the bytes of the line to be written 337 * before the MSHR packet is sent downstream. This works in unison 338 * with the tracking in the MSHR to check if the entire line is 339 * written. The write mode also affects the behaviour on filling 340 * any whole-line writes. Normally the cache allocates the line 341 * when receiving the InvalidateResp, but after seeing enough 342 * consecutive lines we switch to using the tempBlock, and thus 343 * end up not allocating the line, and instead turning the 344 * whole-line write into a writeback straight away. 345 */ 346 WriteAllocator * const writeAllocator; 347 348 /** |
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332 * Temporary cache block for occasional transitory use. We use 333 * the tempBlock to fill when allocation fails (e.g., when there 334 * is an outstanding request that accesses the victim block) or 335 * when we want to avoid allocation (e.g., exclusive caches) 336 */ 337 TempCacheBlk *tempBlock; 338 339 /** --- 816 unchanged lines hidden (view full) --- 1156 * 1157 * We currently don't support checkpointing cache state, so this panics. 1158 */ 1159 void serialize(CheckpointOut &cp) const override; 1160 void unserialize(CheckpointIn &cp) override; 1161 1162}; 1163 | 349 * Temporary cache block for occasional transitory use. We use 350 * the tempBlock to fill when allocation fails (e.g., when there 351 * is an outstanding request that accesses the victim block) or 352 * when we want to avoid allocation (e.g., exclusive caches) 353 */ 354 TempCacheBlk *tempBlock; 355 356 /** --- 816 unchanged lines hidden (view full) --- 1173 * 1174 * We currently don't support checkpointing cache state, so this panics. 1175 */ 1176 void serialize(CheckpointOut &cp) const override; 1177 void unserialize(CheckpointIn &cp) override; 1178 1179}; 1180 |
1181/** 1182 * The write allocator inspects write packets and detects streaming 1183 * patterns. The write allocator supports a single stream where writes 1184 * are expected to access consecutive locations and keeps track of 1185 * size of the area covered by the concecutive writes in byteCount. 1186 * 1187 * 1) When byteCount has surpassed the coallesceLimit the mode 1188 * switches from ALLOCATE to COALESCE where writes should be delayed 1189 * until the whole block is written at which point a single packet 1190 * (whole line write) can service them. 1191 * 1192 * 2) When byteCount has also exceeded the noAllocateLimit (whole 1193 * line) we switch to NO_ALLOCATE when writes should not allocate in 1194 * the cache but rather send a whole line write to the memory below. 1195 */ 1196class WriteAllocator : public SimObject { 1197 public: 1198 WriteAllocator(const WriteAllocatorParams *p) : 1199 SimObject(p), 1200 coalesceLimit(p->coalesce_limit * p->block_size), 1201 noAllocateLimit(p->no_allocate_limit * p->block_size), 1202 delayThreshold(p->delay_threshold) 1203 { 1204 reset(); 1205 } 1206 1207 /** 1208 * Should writes be coalesced? This is true if the mode is set to 1209 * NO_ALLOCATE. 1210 * 1211 * @return return true if the cache should coalesce writes. 1212 */ 1213 bool coalesce() const { 1214 return mode != WriteMode::ALLOCATE; 1215 } 1216 1217 /** 1218 * Should writes allocate? 1219 * 1220 * @return return true if the cache should not allocate for writes. 1221 */ 1222 bool allocate() const { 1223 return mode != WriteMode::NO_ALLOCATE; 1224 } 1225 1226 /** 1227 * Reset the write allocator state, meaning that it allocates for 1228 * writes and has not recorded any information about qualifying 1229 * writes that might trigger a switch to coalescing and later no 1230 * allocation. 1231 */ 1232 void reset() { 1233 mode = WriteMode::ALLOCATE; 1234 byteCount = 0; 1235 nextAddr = 0; 1236 } 1237 1238 /** 1239 * Access whether we need to delay the current write. 1240 * 1241 * @param blk_addr The block address the packet writes to 1242 * @return true if the current packet should be delayed 1243 */ 1244 bool delay(Addr blk_addr) { 1245 if (delayCtr[blk_addr] > 0) { 1246 --delayCtr[blk_addr]; 1247 return true; 1248 } else { 1249 return false; 1250 } 1251 } 1252 1253 /** 1254 * Clear delay counter for the input block 1255 * 1256 * @param blk_addr The accessed cache block 1257 */ 1258 void resetDelay(Addr blk_addr) { 1259 delayCtr.erase(blk_addr); 1260 } 1261 1262 /** 1263 * Update the write mode based on the current write 1264 * packet. This method compares the packet's address with any 1265 * current stream, and updates the tracking and the mode 1266 * accordingly. 1267 * 1268 * @param write_addr Start address of the write request 1269 * @param write_size Size of the write request 1270 * @param blk_addr The block address that this packet writes to 1271 */ 1272 void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr); 1273 1274 private: 1275 /** 1276 * The current mode for write coalescing and allocation, either 1277 * normal operation (ALLOCATE), write coalescing (COALESCE), or 1278 * write coalescing without allocation (NO_ALLOCATE). 1279 */ 1280 enum class WriteMode : char { 1281 ALLOCATE, 1282 COALESCE, 1283 NO_ALLOCATE, 1284 }; 1285 WriteMode mode; 1286 1287 /** Address to match writes against to detect streams. */ 1288 Addr nextAddr; 1289 1290 /** 1291 * Bytes written contiguously. Saturating once we no longer 1292 * allocate. 1293 */ 1294 uint32_t byteCount; 1295 1296 /** 1297 * Limits for when to switch between the different write modes. 1298 */ 1299 const uint32_t coalesceLimit; 1300 const uint32_t noAllocateLimit; 1301 /** 1302 * The number of times the allocator will delay an WriteReq MSHR. 1303 */ 1304 const uint32_t delayThreshold; 1305 1306 /** 1307 * Keep track of the number of times the allocator has delayed an 1308 * WriteReq MSHR. 1309 */ 1310 std::unordered_map<Addr, Counter> delayCtr; 1311}; 1312 |
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1164#endif //__MEM_CACHE_BASE_HH__ | 1313#endif //__MEM_CACHE_BASE_HH__ |