base.hh (12334:e0ab29a34764) | base.hh (12702:27cb33a96e0f) |
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1/* 2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 439 unchanged lines hidden (view full) --- 448 /** The average overall latency of an MSHR miss. */ 449 Stats::Formula overallAvgMshrMissLatency; 450 451 /** The average latency of an MSHR miss, per command and thread. */ 452 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 453 /** The average overall latency of an MSHR miss. */ 454 Stats::Formula overallAvgMshrUncacheableLatency; 455 | 1/* 2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 439 unchanged lines hidden (view full) --- 448 /** The average overall latency of an MSHR miss. */ 449 Stats::Formula overallAvgMshrMissLatency; 450 451 /** The average latency of an MSHR miss, per command and thread. */ 452 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 453 /** The average overall latency of an MSHR miss. */ 454 Stats::Formula overallAvgMshrUncacheableLatency; 455 |
456 /** Number of replacements of valid blocks. */ 457 Stats::Scalar replacements; 458 |
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456 /** 457 * @} 458 */ 459 460 /** 461 * Register stats for this object. 462 */ 463 virtual void regStats() override; --- 146 unchanged lines hidden --- | 459 /** 460 * @} 461 */ 462 463 /** 464 * Register stats for this object. 465 */ 466 virtual void regStats() override; --- 146 unchanged lines hidden --- |