1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 215 unchanged lines hidden (view full) ---

224 }
225
226 /** Block size of this cache */
227 const unsigned blkSize;
228
229 /**
230 * The latency of a hit in this device.
231 */
232 int hitLatency;
233
234 /** The number of targets for each MSHR. */
235 const int numTarget;
236
237 /** Do we forward snoops from mem side port through to cpu side port? */
238 bool forwardSnoops;
239
240 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
241 * never try to forward ownership and similar optimizations to the cpu

--- 320 unchanged lines hidden ---