1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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92 Request_MSHR = MSHRQueue_MSHRs,
93 Request_WB = MSHRQueue_WriteBuffer,
94 Request_PF,
95 NUM_REQUEST_CAUSES
96 };
97
98 protected:
99
100 class CachePort : public SimpleTimingPort
101 {
102 public:
103 BaseCache *cache;
104
105 protected:
106 CachePort(const std::string &_name, BaseCache *_cache,
107 const std::string &_label);
108
109 virtual unsigned deviceBlockSize() const;
110
111 bool recvRetryCommon();
112
113 typedef EventWrapper<Port, &Port::sendRetry>
114 SendRetryEvent;
115
116 const std::string label;
117
118 public:
119 void setBlocked();
120
121 void clearBlocked();
122
123 bool checkFunctional(PacketPtr pkt);
124
125 bool blocked;
126
127 bool mustSendRetry;
128
129 void requestBus(RequestCause cause, Tick time)
130 {
131 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
132 if (!waitingOnRetry) {
133 schedSendEvent(time);
134 }
135 }
136
137 void respond(PacketPtr pkt, Tick time) {
138 schedSendTiming(pkt, time);
139 }
140 };
141
142 CachePort *cpuSidePort;
143 CachePort *memSidePort;
144
145 protected:
146
147 /** Miss status registers */
148 MSHRQueue mshrQueue;
149
150 /** Write/writeback buffer */
151 MSHRQueue writeBuffer;

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