1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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319 /** Total cycle latency of overall MSHR misses. */
320 Stats::Formula overallMshrMissLatency;
321
322 /** Total cycle latency of each MSHR miss, per command and thread. */
323 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
324 /** Total cycle latency of overall MSHR misses. */
325 Stats::Formula overallMshrUncacheableLatency;
326
327 /** The total number of MSHR accesses per command and thread. */
328 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
329 /** The total number of demand MSHR accesses. */
330 Stats::Formula demandMshrAccesses;
331 /** The total number of MSHR accesses. */
332 Stats::Formula overallMshrAccesses;
333
334 /** The miss rate in the MSHRs pre command and thread. */
335 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
336 /** The demand miss rate in the MSHRs. */
337 Stats::Formula demandMshrMissRate;
338 /** The overall miss rate in the MSHRs. */
339 Stats::Formula overallMshrMissRate;
340

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