1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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42#include <string>
43#include <list>
44#include <algorithm>
45
46#include "base/misc.hh"
47#include "base/statistics.hh"
48#include "base/trace.hh"
49#include "base/types.hh"
50#include "mem/cache/mshr_queue.hh"
51#include "mem/mem_object.hh"
52#include "mem/packet.hh"
53#include "mem/tport.hh"
54#include "mem/request.hh"
55#include "params/BaseCache.hh"
56#include "sim/eventq.hh"
57#include "sim/sim_exit.hh"

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214 /** The drain event. */
215 Event *drainEvent;
216
217 /**
218 * The address range to which the cache responds on the CPU side.
219 * Normally this is all possible memory addresses. */
220 Range<Addr> addrRange;
221
222 public:
223 // Statistics
224 /**
225 * @addtogroup CacheStatistics
226 * @{
227 */
228
229 /** Number of hits per thread for each type of command. @sa Packet::Command */
230 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];

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476 }
477
478 virtual unsigned int drain(Event *de);
479
480 virtual bool inCache(Addr addr) = 0;
481
482 virtual bool inMissQueue(Addr addr) = 0;
483
484 void incMissCount(PacketPtr pkt)
485 {
486 misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
487
488 if (missCount) {
489 --missCount;
490 if (missCount == 0)
491 exitSimLoop("A cache reached the maximum miss count");
492 }
493 }
494
495};
496
497#endif //__BASE_CACHE_HH__