1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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95
96 class CachePort : public SimpleTimingPort
97 {
98 public:
99 BaseCache *cache;
100
101 protected:
102 CachePort(const std::string &_name, BaseCache *_cache,
103 const std::string &_label,
104 std::vector<Range<Addr> > filter_ranges);
105
106 virtual void recvStatusChange(Status status);
107
108 virtual int deviceBlockSize();
109
110 bool recvRetryCommon();
111
112 typedef EventWrapper<Port, &Port::sendRetry>

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124 bool checkFunctional(PacketPtr pkt);
125
126 CachePort *otherPort;
127
128 bool blocked;
129
130 bool mustSendRetry;
131
132 /** filter ranges */
133 std::vector<Range<Addr> > filterRanges;
134
135 void requestBus(RequestCause cause, Tick time)
136 {
137 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
138 if (!waitingOnRetry) {
139 schedSendEvent(time);
140 }
141 }
142

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189 /**
190 * The latency of a hit in this device.
191 */
192 int hitLatency;
193
194 /** The number of targets for each MSHR. */
195 const int numTarget;
196
197 /** Increasing order number assigned to each incoming request. */
198 uint64_t order;
199
200 /**
201 * Bit vector of the blocking reasons for the access path.
202 * @sa #BlockedCause
203 */
204 uint8_t blocked;
205
206 /** Stores time the cache blocked for statistics. */
207 Tick blockedCycle;
208
209 /** Pointer to the MSHR that has no targets. */
210 MSHR *noTargetMSHR;
211
212 /** The number of misses to trigger an exit event. */
213 Counter missCount;
214
215 /** The drain event. */
216 Event *drainEvent;
217
218 public:
219 // Statistics
220 /**
221 * @addtogroup CacheStatistics
222 * @{
223 */
224
225 /** Number of hits per thread for each type of command. @sa Packet::Command */

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372 {
373 return blkSize;
374 }
375
376
377 Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); }
378
379
380 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
381 {
382 assert(!pkt->req->isUncacheable());
383 return allocateBufferInternal(&mshrQueue,
384 blockAlign(pkt->getAddr()), blkSize,
385 pkt, time, requestBus);
386 }
387

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