1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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68#include "mem/cache/tags/base.hh"
69#include "mem/cache/write_queue.hh"
70#include "mem/cache/write_queue_entry.hh"
71#include "mem/mem_object.hh"
72#include "mem/packet.hh"
73#include "mem/packet_queue.hh"
74#include "mem/qport.hh"
75#include "mem/request.hh"
76#include "sim/eventq.hh"
77#include "sim/serialize.hh"
78#include "sim/sim_exit.hh"
79#include "sim/system.hh"
80
81class BaseMasterPort;
82class BasePrefetcher;
83class BaseSlavePort;

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324 BasePrefetcher *prefetcher;
325
326 /**
327 * Notify the prefetcher on every access, not just misses.
328 */
329 const bool prefetchOnAccess;
330
331 /**
332 * Temporary cache block for occasional transitory use. We use
333 * the tempBlock to fill when allocation fails (e.g., when there
334 * is an outstanding request that accesses the victim block) or
335 * when we want to avoid allocation (e.g., exclusive caches)
336 */
337 TempCacheBlk *tempBlock;
338
339 /**

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1156 *
1157 * We currently don't support checkpointing cache state, so this panics.
1158 */
1159 void serialize(CheckpointOut &cp) const override;
1160 void unserialize(CheckpointIn &cp) override;
1161
1162};
1163
1164#endif //__MEM_CACHE_BASE_HH__