1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
--- 24 unchanged lines hidden (view full) ---
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __MEM_CACHE_BASE_HH__
51#define __MEM_CACHE_BASE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/logging.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/cache/write_queue.hh"
66#include "mem/mem_object.hh"
67#include "mem/packet.hh"
68#include "mem/qport.hh"
69#include "mem/request.hh"
70#include "params/BaseCache.hh"
71#include "sim/eventq.hh"
72#include "sim/full_system.hh"
73#include "sim/sim_exit.hh"
74#include "sim/system.hh"
75
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 protected:
82 /**
83 * Indexes to enumerate the MSHR queues.
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136 * Memory-side port always snoops.
137 *
138 * @return always true
139 */
140 virtual bool isSnooping() const { return true; }
141 };
142
143 /**
144 * A cache slave port is used for the CPU-side port of the cache,
145 * and it is basically a simple timing port that uses a transmit
146 * list for responses to the CPU (or connected master). In
147 * addition, it has the functionality to block the port for
148 * incoming requests. If blocked, the port will issue a retry once
149 * unblocked.
150 */
151 class CacheSlavePort : public QueuedSlavePort
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176 private:
177
178 void processSendRetry();
179
180 EventFunctionWrapper sendRetryEvent;
181
182 };
183
184 CacheSlavePort *cpuSidePort;
185 CacheMasterPort *memSidePort;
186
187 protected:
188
189 /** Miss status registers */
190 MSHRQueue mshrQueue;
191
192 /** Write/writeback buffer */
193 WriteQueue writeBuffer;
194
195 /**
196 * Mark a request as in service (sent downstream in the memory
197 * system), effectively making this MSHR the ordering point.
198 */
199 void markInService(MSHR *mshr, bool pending_modified_resp)
200 {
201 bool wasFull = mshrQueue.isFull();
202 mshrQueue.markInService(mshr, pending_modified_resp);
203
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212 writeBuffer.markInService(entry);
213
214 if (wasFull && !writeBuffer.isFull()) {
215 clearBlocked(Blocked_NoWBBuffers);
216 }
217 }
218
219 /**
220 * Determine if we should allocate on a fill or not.
221 *
222 * @param cmd Packet command being added as an MSHR target
223 *
224 * @return Whether we should allocate on a fill or not
225 */
226 virtual bool allocOnFill(MemCmd cmd) const = 0;
227
228 /**
229 * Write back dirty blocks in the cache using functional accesses.
230 */
231 virtual void memWriteback() override = 0;
232 /**
233 * Invalidates all blocks in the cache.
234 *
235 * @warn Dirty cache lines will not be written back to
236 * memory. Make sure to call functionalWriteback() first if you
237 * want the to write them to memory.
238 */
239 virtual void memInvalidate() override = 0;
240 /**
241 * Determine if there are any dirty blocks in the cache.
242 *
243 * \return true if at least one block is dirty, false otherwise.
244 */
245 virtual bool isDirty() const = 0;
246
247 /**
248 * Determine if an address is in the ranges covered by this
249 * cache. This is useful to filter snoops.
250 *
251 * @param addr Address to check against
252 *
253 * @return If the address in question is in range
254 */
255 bool inRange(Addr addr) const;
256
257 /** Block size of this cache */
258 const unsigned blkSize;
259
260 /**
261 * The latency of tag lookup of a cache. It occurs when there is
262 * an access to the cache.
263 */
264 const Cycles lookupLatency;
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288
289 /** The number of targets for each MSHR. */
290 const int numTarget;
291
292 /** Do we forward snoops from mem side port through to cpu side port? */
293 bool forwardSnoops;
294
295 /**
296 * Is this cache read only, for example the instruction cache, or
297 * table-walker cache. A cache that is read only should never see
298 * any writes, and should never get any dirty data (and hence
299 * never have to do any writebacks).
300 */
301 const bool isReadOnly;
302
303 /**
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458
459 /**
460 * @}
461 */
462
463 /**
464 * Register stats for this object.
465 */
466 virtual void regStats() override;
467
468 public:
469 BaseCache(const BaseCacheParams *p, unsigned blk_size);
470 ~BaseCache() {}
471
472 virtual void init() override;
473
474 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
475 PortID idx = InvalidPortID) override;
476 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
477 PortID idx = InvalidPortID) override;
478
479 /**
480 * Query block size of a cache.
481 * @return The block size
482 */
483 unsigned
484 getBlockSize() const
485 {
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543 * @param cause The reason for the cache blocking.
544 */
545 void setBlocked(BlockedCause cause)
546 {
547 uint8_t flag = 1 << cause;
548 if (blocked == 0) {
549 blocked_causes[cause]++;
550 blockedCycle = curCycle();
551 cpuSidePort->setBlocked();
552 }
553 blocked |= flag;
554 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
555 }
556
557 /**
558 * Marks the cache as unblocked for the given cause. This also clears the
559 * blocked flags in the appropriate interfaces.
560 * @param cause The newly unblocked cause.
561 * @warning Calling this function can cause a blocked request on the bus to
562 * access the cache. The cache must be in a state to handle that request.
563 */
564 void clearBlocked(BlockedCause cause)
565 {
566 uint8_t flag = 1 << cause;
567 blocked &= ~flag;
568 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
569 if (blocked == 0) {
570 blocked_cycles[cause] += curCycle() - blockedCycle;
571 cpuSidePort->clearBlocked();
572 }
573 }
574
575 /**
576 * Schedule a send event for the memory-side port. If already
577 * scheduled, this may reschedule the event at an earlier
578 * time. When the specified time is reached, the port is free to
579 * send either a response, a request, or a prefetch request.
580 *
581 * @param time The time when to attempt sending a packet.
582 */
583 void schedMemSideSendEvent(Tick time)
584 {
585 memSidePort->schedSendEvent(time);
586 }
587
588 virtual bool inCache(Addr addr, bool is_secure) const = 0;
589
590 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
591
592 void incMissCount(PacketPtr pkt)
593 {
594 assert(pkt->req->masterId() < system->maxMasters());
595 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
596 pkt->req->incAccessDepth();
597 if (missCount) {
598 --missCount;
599 if (missCount == 0)
600 exitSimLoop("A cache reached the maximum miss count");
601 }
602 }
603 void incHitCount(PacketPtr pkt)
604 {
605 assert(pkt->req->masterId() < system->maxMasters());
606 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
607
608 }
609
610};
611
612#endif //__MEM_CACHE_BASE_HH__
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
--- 24 unchanged lines hidden (view full) ---
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __MEM_CACHE_BASE_HH__
51#define __MEM_CACHE_BASE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/logging.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/cache/write_queue.hh"
66#include "mem/mem_object.hh"
67#include "mem/packet.hh"
68#include "mem/qport.hh"
69#include "mem/request.hh"
70#include "params/BaseCache.hh"
71#include "sim/eventq.hh"
72#include "sim/full_system.hh"
73#include "sim/sim_exit.hh"
74#include "sim/system.hh"
75
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 protected:
82 /**
83 * Indexes to enumerate the MSHR queues.
--- 52 unchanged lines hidden (view full) ---
136 * Memory-side port always snoops.
137 *
138 * @return always true
139 */
140 virtual bool isSnooping() const { return true; }
141 };
142
143 /**
144 * A cache slave port is used for the CPU-side port of the cache,
145 * and it is basically a simple timing port that uses a transmit
146 * list for responses to the CPU (or connected master). In
147 * addition, it has the functionality to block the port for
148 * incoming requests. If blocked, the port will issue a retry once
149 * unblocked.
150 */
151 class CacheSlavePort : public QueuedSlavePort
--- 24 unchanged lines hidden (view full) ---
176 private:
177
178 void processSendRetry();
179
180 EventFunctionWrapper sendRetryEvent;
181
182 };
183
184 CacheSlavePort *cpuSidePort;
185 CacheMasterPort *memSidePort;
186
187 protected:
188
189 /** Miss status registers */
190 MSHRQueue mshrQueue;
191
192 /** Write/writeback buffer */
193 WriteQueue writeBuffer;
194
195 /**
196 * Mark a request as in service (sent downstream in the memory
197 * system), effectively making this MSHR the ordering point.
198 */
199 void markInService(MSHR *mshr, bool pending_modified_resp)
200 {
201 bool wasFull = mshrQueue.isFull();
202 mshrQueue.markInService(mshr, pending_modified_resp);
203
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212 writeBuffer.markInService(entry);
213
214 if (wasFull && !writeBuffer.isFull()) {
215 clearBlocked(Blocked_NoWBBuffers);
216 }
217 }
218
219 /**
220 * Determine if we should allocate on a fill or not.
221 *
222 * @param cmd Packet command being added as an MSHR target
223 *
224 * @return Whether we should allocate on a fill or not
225 */
226 virtual bool allocOnFill(MemCmd cmd) const = 0;
227
228 /**
229 * Write back dirty blocks in the cache using functional accesses.
230 */
231 virtual void memWriteback() override = 0;
232 /**
233 * Invalidates all blocks in the cache.
234 *
235 * @warn Dirty cache lines will not be written back to
236 * memory. Make sure to call functionalWriteback() first if you
237 * want the to write them to memory.
238 */
239 virtual void memInvalidate() override = 0;
240 /**
241 * Determine if there are any dirty blocks in the cache.
242 *
243 * \return true if at least one block is dirty, false otherwise.
244 */
245 virtual bool isDirty() const = 0;
246
247 /**
248 * Determine if an address is in the ranges covered by this
249 * cache. This is useful to filter snoops.
250 *
251 * @param addr Address to check against
252 *
253 * @return If the address in question is in range
254 */
255 bool inRange(Addr addr) const;
256
257 /** Block size of this cache */
258 const unsigned blkSize;
259
260 /**
261 * The latency of tag lookup of a cache. It occurs when there is
262 * an access to the cache.
263 */
264 const Cycles lookupLatency;
--- 23 unchanged lines hidden (view full) ---
288
289 /** The number of targets for each MSHR. */
290 const int numTarget;
291
292 /** Do we forward snoops from mem side port through to cpu side port? */
293 bool forwardSnoops;
294
295 /**
296 * Is this cache read only, for example the instruction cache, or
297 * table-walker cache. A cache that is read only should never see
298 * any writes, and should never get any dirty data (and hence
299 * never have to do any writebacks).
300 */
301 const bool isReadOnly;
302
303 /**
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458
459 /**
460 * @}
461 */
462
463 /**
464 * Register stats for this object.
465 */
466 virtual void regStats() override;
467
468 public:
469 BaseCache(const BaseCacheParams *p, unsigned blk_size);
470 ~BaseCache() {}
471
472 virtual void init() override;
473
474 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
475 PortID idx = InvalidPortID) override;
476 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
477 PortID idx = InvalidPortID) override;
478
479 /**
480 * Query block size of a cache.
481 * @return The block size
482 */
483 unsigned
484 getBlockSize() const
485 {
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543 * @param cause The reason for the cache blocking.
544 */
545 void setBlocked(BlockedCause cause)
546 {
547 uint8_t flag = 1 << cause;
548 if (blocked == 0) {
549 blocked_causes[cause]++;
550 blockedCycle = curCycle();
551 cpuSidePort->setBlocked();
552 }
553 blocked |= flag;
554 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
555 }
556
557 /**
558 * Marks the cache as unblocked for the given cause. This also clears the
559 * blocked flags in the appropriate interfaces.
560 * @param cause The newly unblocked cause.
561 * @warning Calling this function can cause a blocked request on the bus to
562 * access the cache. The cache must be in a state to handle that request.
563 */
564 void clearBlocked(BlockedCause cause)
565 {
566 uint8_t flag = 1 << cause;
567 blocked &= ~flag;
568 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
569 if (blocked == 0) {
570 blocked_cycles[cause] += curCycle() - blockedCycle;
571 cpuSidePort->clearBlocked();
572 }
573 }
574
575 /**
576 * Schedule a send event for the memory-side port. If already
577 * scheduled, this may reschedule the event at an earlier
578 * time. When the specified time is reached, the port is free to
579 * send either a response, a request, or a prefetch request.
580 *
581 * @param time The time when to attempt sending a packet.
582 */
583 void schedMemSideSendEvent(Tick time)
584 {
585 memSidePort->schedSendEvent(time);
586 }
587
588 virtual bool inCache(Addr addr, bool is_secure) const = 0;
589
590 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
591
592 void incMissCount(PacketPtr pkt)
593 {
594 assert(pkt->req->masterId() < system->maxMasters());
595 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
596 pkt->req->incAccessDepth();
597 if (missCount) {
598 --missCount;
599 if (missCount == 0)
600 exitSimLoop("A cache reached the maximum miss count");
601 }
602 }
603 void incHitCount(PacketPtr pkt)
604 {
605 assert(pkt->req->masterId() < system->maxMasters());
606 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
607
608 }
609
610};
611
612#endif //__MEM_CACHE_BASE_HH__