1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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205 PacketPtr pkt, Tick time,
206 bool sched_send)
207 {
208 // check that the address is block aligned since we rely on
209 // this in a number of places when checking for matches and
210 // overlap
211 assert(addr == blockAlign(addr));
212
213 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
214
215 if (mq->isFull()) {
216 setBlocked((BlockedCause)mq->index);
217 }
218
219 if (sched_send)
220 // schedule the send
221 schedMemSideSendEvent(time);

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229 bool wasFull = mq->isFull();
230 mq->markInService(mshr, pending_dirty_resp);
231 if (wasFull && !mq->isFull()) {
232 clearBlocked((BlockedCause)mq->index);
233 }
234 }
235
236 /**
237 * Write back dirty blocks in the cache using functional accesses.
238 */
239 virtual void memWriteback() = 0;
240 /**
241 * Invalidates all blocks in the cache.
242 *
243 * @warn Dirty cache lines will not be written back to
244 * memory. Make sure to call functionalWriteback() first if you

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