1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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197 protected:
198
199 /** Miss status registers */
200 MSHRQueue mshrQueue;
201
202 /** Write/writeback buffer */
203 MSHRQueue writeBuffer;
204
205 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
206 PacketPtr pkt, Tick time, bool requestBus)
207 {
208 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
209
210 if (mq->isFull()) {
211 setBlocked((BlockedCause)mq->index);
212 }

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246 * \return true if at least one block is dirty, false otherwise.
247 */
248 virtual bool isDirty() const = 0;
249
250 /** Block size of this cache */
251 const unsigned blkSize;
252
253 /**
254 * The latency of a hit in this device.
255 */
256 const Cycles hitLatency;
257
258 /**
259 * The latency of sending reponse to its upper level cache/core on a
260 * linefill. In most contemporary processors, the return path on a cache
261 * miss is much quicker that the hit latency. The responseLatency parameter
262 * tries to capture this latency.
263 */
264 const Cycles responseLatency;
265
266 /** The number of targets for each MSHR. */
267 const int numTarget;
268
269 /** Do we forward snoops from mem side port through to cpu side port? */
270 const bool forwardSnoops;
271

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