1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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177 SlavePacketQueue queue;
178
179 bool blocked;
180
181 bool mustSendRetry;
182
183 private:
184
185 EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
186
187 };
188
189 CacheSlavePort *cpuSidePort;
190 CacheMasterPort *memSidePort;
191
192 protected:
193
194 /** Miss status registers */

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