1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 196 unchanged lines hidden (view full) ---

205 PacketPtr pkt, Tick time,
206 bool sched_send)
207 {
208 // check that the address is block aligned since we rely on
209 // this in a number of places when checking for matches and
210 // overlap
211 assert(addr == blockAlign(addr));
212
213 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++,
214 allocOnFill(pkt->cmd));
215
216 if (mq->isFull()) {
217 setBlocked((BlockedCause)mq->index);
218 }
219
220 if (sched_send)
221 // schedule the send
222 schedMemSideSendEvent(time);

--- 7 unchanged lines hidden (view full) ---

230 bool wasFull = mq->isFull();
231 mq->markInService(mshr, pending_dirty_resp);
232 if (wasFull && !mq->isFull()) {
233 clearBlocked((BlockedCause)mq->index);
234 }
235 }
236
237 /**
238 * Determine if we should allocate on a fill or not.
239 *
240 * @param cmd Packet command being added as an MSHR target
241 *
242 * @return Whether we should allocate on a fill or not
243 */
244 virtual bool allocOnFill(MemCmd cmd) const = 0;
245
246 /**
247 * Write back dirty blocks in the cache using functional accesses.
248 */
249 virtual void memWriteback() = 0;
250 /**
251 * Invalidates all blocks in the cache.
252 *
253 * @warn Dirty cache lines will not be written back to
254 * memory. Make sure to call functionalWriteback() first if you

--- 358 unchanged lines hidden ---