1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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177 SlavePacketQueue queue;
178
179 bool blocked;
180
181 bool mustSendRetry;
182
183 private:
184
185 void processSendRetry();
186
187 EventWrapper<CacheSlavePort,
188 &CacheSlavePort::processSendRetry> sendRetryEvent;
189
190 };
191
192 CacheSlavePort *cpuSidePort;
193 CacheMasterPort *memSidePort;
194
195 protected:
196
197 /** Miss status registers */

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