base.cc (9796:485399270ca1) base.cc (9814:7ad2b0186a32)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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66{
67}
68
69BaseCache::BaseCache(const Params *p)
70 : MemObject(p),
71 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
72 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
73 MSHRQueue_WriteBuffer),
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 57 unchanged lines hidden (view full) ---

66{
67}
68
69BaseCache::BaseCache(const Params *p)
70 : MemObject(p),
71 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
72 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
73 MSHRQueue_WriteBuffer),
74 blkSize(p->block_size),
74 blkSize(p->system->cacheLineSize()),
75 hitLatency(p->hit_latency),
76 responseLatency(p->response_latency),
77 numTarget(p->tgts_per_mshr),
78 forwardSnoops(p->forward_snoops),
79 isTopLevel(p->is_top_level),
80 blocked(0),
81 noTargetMSHR(NULL),
82 missCount(p->max_miss_count),

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768
769 setDrainState(Drainable::Drained);
770 return 0;
771}
772
773BaseCache *
774BaseCacheParams::create()
775{
75 hitLatency(p->hit_latency),
76 responseLatency(p->response_latency),
77 numTarget(p->tgts_per_mshr),
78 forwardSnoops(p->forward_snoops),
79 isTopLevel(p->is_top_level),
80 blocked(0),
81 noTargetMSHR(NULL),
82 missCount(p->max_miss_count),

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768
769 setDrainState(Drainable::Drained);
770 return 0;
771}
772
773BaseCache *
774BaseCacheParams::create()
775{
776 unsigned numSets = size / (assoc * block_size);
776 unsigned numSets = size / (assoc * system->cacheLineSize());
777
778 assert(tags);
779
780 if (dynamic_cast<FALRU*>(tags)) {
781 if (numSets != 1)
782 fatal("Got FALRU tags with more than one set\n");
783 return new Cache<FALRU>(this);
784 } else if (dynamic_cast<LRU*>(tags)) {
785 if (numSets == 1)
786 warn("Consider using FALRU tags for a fully associative cache\n");
787 return new Cache<LRU>(this);
788 } else {
789 fatal("No suitable tags selected\n");
790 }
791}
777
778 assert(tags);
779
780 if (dynamic_cast<FALRU*>(tags)) {
781 if (numSets != 1)
782 fatal("Got FALRU tags with more than one set\n");
783 return new Cache<FALRU>(this);
784 } else if (dynamic_cast<LRU*>(tags)) {
785 if (numSets == 1)
786 warn("Consider using FALRU tags for a fully associative cache\n");
787 return new Cache<LRU>(this);
788 } else {
789 fatal("No suitable tags selected\n");
790 }
791}