base.cc (9347:b02075171b57) | base.cc (9418:9923a5ab8c13) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 67 unchanged lines hidden (view full) --- 76 isTopLevel(p->is_top_level), 77 blocked(0), 78 noTargetMSHR(NULL), 79 missCount(p->max_miss_count), 80 drainManager(NULL), 81 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 82 system(p->system) 83{ | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 67 unchanged lines hidden (view full) --- 76 isTopLevel(p->is_top_level), 77 blocked(0), 78 noTargetMSHR(NULL), 79 missCount(p->max_miss_count), 80 drainManager(NULL), 81 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 82 system(p->system) 83{ |
84 // ensure the clock is not running at an unreasonable clock speed 85 if (clock == 1) 86 panic("Cache %s has a cycle time of 1 tick. Specify a clock.\n", 87 name()); | |
88} 89 90void 91BaseCache::CacheSlavePort::setBlocked() 92{ 93 assert(!blocked); 94 DPRINTF(CachePort, "Cache port %s blocking new requests\n", name()); 95 blocked = true; --- 673 unchanged lines hidden --- | 84} 85 86void 87BaseCache::CacheSlavePort::setBlocked() 88{ 89 assert(!blocked); 90 DPRINTF(CachePort, "Cache port %s blocking new requests\n", name()); 91 blocked = true; --- 673 unchanged lines hidden --- |