base.cc (8833:2870638642bd) base.cc (8856:241ee47b0dc6)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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37#include "cpu/smt.hh"
38#include "debug/Cache.hh"
39#include "mem/cache/base.hh"
40#include "mem/cache/mshr.hh"
41#include "sim/full_system.hh"
42
43using namespace std;
44
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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49#include "cpu/smt.hh"
50#include "debug/Cache.hh"
51#include "mem/cache/base.hh"
52#include "mem/cache/mshr.hh"
53#include "sim/full_system.hh"
54
55using namespace std;
56
45BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
46 const std::string &_label)
47 : SimpleTimingPort(_name, _cache), cache(_cache),
48 label(_label), blocked(false), mustSendRetry(false)
57BaseCache::CacheMasterPort::CacheMasterPort(const std::string &_name,
58 BaseCache *_cache,
59 const std::string &_label)
60 : SimpleTimingPort(_name, _cache, _label)
49{
50}
51
61{
62}
63
64BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
65 BaseCache *_cache,
66 const std::string &_label)
67 : SimpleTimingPort(_name, _cache, _label), blocked(false),
68 mustSendRetry(false), sendRetryEvent(this)
69{
70}
52
53BaseCache::BaseCache(const Params *p)
54 : MemObject(p),
55 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
56 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
57 MSHRQueue_WriteBuffer),
58 blkSize(p->block_size),
59 hitLatency(p->latency),

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64 noTargetMSHR(NULL),
65 missCount(p->max_miss_count),
66 drainEvent(NULL),
67 addrRange(p->addr_range),
68 system(p->system)
69{
70}
71
71
72BaseCache::BaseCache(const Params *p)
73 : MemObject(p),
74 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
75 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
76 MSHRQueue_WriteBuffer),
77 blkSize(p->block_size),
78 hitLatency(p->latency),

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83 noTargetMSHR(NULL),
84 missCount(p->max_miss_count),
85 drainEvent(NULL),
86 addrRange(p->addr_range),
87 system(p->system)
88{
89}
90
72
73bool
74BaseCache::CachePort::checkFunctional(PacketPtr pkt)
75{
76 pkt->pushLabel(label);
77 bool done = SimpleTimingPort::checkFunctional(pkt);
78 pkt->popLabel();
79 return done;
80}
81
82
83unsigned
84BaseCache::CachePort::deviceBlockSize() const
85{
86 return cache->getBlockSize();
87}
88
89
90bool
91BaseCache::CachePort::recvRetryCommon()
92{
93 assert(waitingOnRetry);
94 waitingOnRetry = false;
95 return false;
96}
97
98
99void
91void
100BaseCache::CachePort::setBlocked()
92BaseCache::CacheSlavePort::setBlocked()
101{
102 assert(!blocked);
93{
94 assert(!blocked);
103 DPRINTF(Cache, "Cache Blocking\n");
95 DPRINTF(CachePort, "Cache port %s blocking new requests\n", name());
104 blocked = true;
96 blocked = true;
105 //Clear the retry flag
106 mustSendRetry = false;
107}
108
109void
97}
98
99void
110BaseCache::CachePort::clearBlocked()
100BaseCache::CacheSlavePort::clearBlocked()
111{
112 assert(blocked);
101{
102 assert(blocked);
113 DPRINTF(Cache, "Cache Unblocking\n");
103 DPRINTF(CachePort, "Cache port %s accepting new requests\n", name());
114 blocked = false;
104 blocked = false;
115 if (mustSendRetry)
116 {
117 DPRINTF(Cache, "Cache Sending Retry\n");
105 if (mustSendRetry) {
106 DPRINTF(CachePort, "Cache port %s sending retry\n", name());
118 mustSendRetry = false;
107 mustSendRetry = false;
119 SendRetryEvent *ev = new SendRetryEvent(this, true);
120 // @TODO: need to find a better time (next bus cycle?)
108 // @TODO: need to find a better time (next bus cycle?)
121 cache->schedule(ev, curTick() + 1);
109 owner->schedule(sendRetryEvent, curTick() + 1);
122 }
123}
124
125
126void
127BaseCache::init()
128{
110 }
111}
112
113
114void
115BaseCache::init()
116{
129 if (!cpuSidePort || !memSidePort)
130 panic("Cache not hooked up on both sides\n");
117 if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
118 panic("Cache %s not hooked up on both sides\n", name());
131 cpuSidePort->sendRangeChange();
132}
133
134
135void
136BaseCache::regStats()
137{
138 using namespace Stats;

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120}
121
122
123void
124BaseCache::regStats()
125{
126 using namespace Stats;

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