base.cc (8809:bb10807da889) base.cc (8833:2870638642bd)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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60 numTarget(p->tgts_per_mshr),
61 forwardSnoops(p->forward_snoops),
62 isTopLevel(p->is_top_level),
63 blocked(0),
64 noTargetMSHR(NULL),
65 missCount(p->max_miss_count),
66 drainEvent(NULL),
67 addrRange(p->addr_range),
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 51 unchanged lines hidden (view full) ---

60 numTarget(p->tgts_per_mshr),
61 forwardSnoops(p->forward_snoops),
62 isTopLevel(p->is_top_level),
63 blocked(0),
64 noTargetMSHR(NULL),
65 missCount(p->max_miss_count),
66 drainEvent(NULL),
67 addrRange(p->addr_range),
68 _numCpus(p->num_cpus)
68 system(p->system)
69{
70}
71
72
73bool
74BaseCache::CachePort::checkFunctional(PacketPtr pkt)
75{
76 pkt->pushLabel(label);

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138 using namespace Stats;
139
140 // Hit statistics
141 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
142 MemCmd cmd(access_idx);
143 const string &cstr = cmd.toString();
144
145 hits[access_idx]
69{
70}
71
72
73bool
74BaseCache::CachePort::checkFunctional(PacketPtr pkt)
75{
76 pkt->pushLabel(label);

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138 using namespace Stats;
139
140 // Hit statistics
141 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
142 MemCmd cmd(access_idx);
143 const string &cstr = cmd.toString();
144
145 hits[access_idx]
146 .init(FullSystem ? (_numCpus + 1) : _numCpus)
146 .init(system->maxMasters())
147 .name(name() + "." + cstr + "_hits")
148 .desc("number of " + cstr + " hits")
149 .flags(total | nozero | nonan)
150 ;
147 .name(name() + "." + cstr + "_hits")
148 .desc("number of " + cstr + " hits")
149 .flags(total | nozero | nonan)
150 ;
151 for (int i = 0; i < system->maxMasters(); i++) {
152 hits[access_idx].subname(i, system->getMasterName(i));
153 }
151 }
152
153// These macros make it easier to sum the right subset of commands and
154// to change the subset of commands that are considered "demand" vs
155// "non-demand"
156#define SUM_DEMAND(s) \
157 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq])
158
159// should writebacks be included here? prior code was inconsistent...
160#define SUM_NON_DEMAND(s) \
161 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
162
163 demandHits
164 .name(name() + ".demand_hits")
165 .desc("number of demand (read+write) hits")
154 }
155
156// These macros make it easier to sum the right subset of commands and
157// to change the subset of commands that are considered "demand" vs
158// "non-demand"
159#define SUM_DEMAND(s) \
160 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq])
161
162// should writebacks be included here? prior code was inconsistent...
163#define SUM_NON_DEMAND(s) \
164 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
165
166 demandHits
167 .name(name() + ".demand_hits")
168 .desc("number of demand (read+write) hits")
166 .flags(total)
169 .flags(total | nozero | nonan)
167 ;
168 demandHits = SUM_DEMAND(hits);
170 ;
171 demandHits = SUM_DEMAND(hits);
172 for (int i = 0; i < system->maxMasters(); i++) {
173 demandHits.subname(i, system->getMasterName(i));
174 }
169
170 overallHits
171 .name(name() + ".overall_hits")
172 .desc("number of overall hits")
175
176 overallHits
177 .name(name() + ".overall_hits")
178 .desc("number of overall hits")
173 .flags(total)
179 .flags(total | nozero | nonan)
174 ;
175 overallHits = demandHits + SUM_NON_DEMAND(hits);
180 ;
181 overallHits = demandHits + SUM_NON_DEMAND(hits);
182 for (int i = 0; i < system->maxMasters(); i++) {
183 overallHits.subname(i, system->getMasterName(i));
184 }
176
177 // Miss statistics
178 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
179 MemCmd cmd(access_idx);
180 const string &cstr = cmd.toString();
181
182 misses[access_idx]
185
186 // Miss statistics
187 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
188 MemCmd cmd(access_idx);
189 const string &cstr = cmd.toString();
190
191 misses[access_idx]
183 .init(FullSystem ? (_numCpus + 1) : _numCpus)
192 .init(system->maxMasters())
184 .name(name() + "." + cstr + "_misses")
185 .desc("number of " + cstr + " misses")
186 .flags(total | nozero | nonan)
187 ;
193 .name(name() + "." + cstr + "_misses")
194 .desc("number of " + cstr + " misses")
195 .flags(total | nozero | nonan)
196 ;
197 for (int i = 0; i < system->maxMasters(); i++) {
198 misses[access_idx].subname(i, system->getMasterName(i));
199 }
188 }
189
190 demandMisses
191 .name(name() + ".demand_misses")
192 .desc("number of demand (read+write) misses")
200 }
201
202 demandMisses
203 .name(name() + ".demand_misses")
204 .desc("number of demand (read+write) misses")
193 .flags(total)
205 .flags(total | nozero | nonan)
194 ;
195 demandMisses = SUM_DEMAND(misses);
206 ;
207 demandMisses = SUM_DEMAND(misses);
208 for (int i = 0; i < system->maxMasters(); i++) {
209 demandMisses.subname(i, system->getMasterName(i));
210 }
196
197 overallMisses
198 .name(name() + ".overall_misses")
199 .desc("number of overall misses")
211
212 overallMisses
213 .name(name() + ".overall_misses")
214 .desc("number of overall misses")
200 .flags(total)
215 .flags(total | nozero | nonan)
201 ;
202 overallMisses = demandMisses + SUM_NON_DEMAND(misses);
216 ;
217 overallMisses = demandMisses + SUM_NON_DEMAND(misses);
218 for (int i = 0; i < system->maxMasters(); i++) {
219 overallMisses.subname(i, system->getMasterName(i));
220 }
203
204 // Miss latency statistics
205 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
206 MemCmd cmd(access_idx);
207 const string &cstr = cmd.toString();
208
209 missLatency[access_idx]
221
222 // Miss latency statistics
223 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
224 MemCmd cmd(access_idx);
225 const string &cstr = cmd.toString();
226
227 missLatency[access_idx]
210 .init(maxThreadsPerCPU)
228 .init(system->maxMasters())
211 .name(name() + "." + cstr + "_miss_latency")
212 .desc("number of " + cstr + " miss cycles")
213 .flags(total | nozero | nonan)
214 ;
229 .name(name() + "." + cstr + "_miss_latency")
230 .desc("number of " + cstr + " miss cycles")
231 .flags(total | nozero | nonan)
232 ;
233 for (int i = 0; i < system->maxMasters(); i++) {
234 missLatency[access_idx].subname(i, system->getMasterName(i));
235 }
215 }
216
217 demandMissLatency
218 .name(name() + ".demand_miss_latency")
219 .desc("number of demand (read+write) miss cycles")
236 }
237
238 demandMissLatency
239 .name(name() + ".demand_miss_latency")
240 .desc("number of demand (read+write) miss cycles")
220 .flags(total)
241 .flags(total | nozero | nonan)
221 ;
222 demandMissLatency = SUM_DEMAND(missLatency);
242 ;
243 demandMissLatency = SUM_DEMAND(missLatency);
244 for (int i = 0; i < system->maxMasters(); i++) {
245 demandMissLatency.subname(i, system->getMasterName(i));
246 }
223
224 overallMissLatency
225 .name(name() + ".overall_miss_latency")
226 .desc("number of overall miss cycles")
247
248 overallMissLatency
249 .name(name() + ".overall_miss_latency")
250 .desc("number of overall miss cycles")
227 .flags(total)
251 .flags(total | nozero | nonan)
228 ;
229 overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
252 ;
253 overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
254 for (int i = 0; i < system->maxMasters(); i++) {
255 overallMissLatency.subname(i, system->getMasterName(i));
256 }
230
231 // access formulas
232 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
233 MemCmd cmd(access_idx);
234 const string &cstr = cmd.toString();
235
236 accesses[access_idx]
237 .name(name() + "." + cstr + "_accesses")
238 .desc("number of " + cstr + " accesses(hits+misses)")
239 .flags(total | nozero | nonan)
240 ;
257
258 // access formulas
259 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
260 MemCmd cmd(access_idx);
261 const string &cstr = cmd.toString();
262
263 accesses[access_idx]
264 .name(name() + "." + cstr + "_accesses")
265 .desc("number of " + cstr + " accesses(hits+misses)")
266 .flags(total | nozero | nonan)
267 ;
241
242 accesses[access_idx] = hits[access_idx] + misses[access_idx];
268 accesses[access_idx] = hits[access_idx] + misses[access_idx];
269
270 for (int i = 0; i < system->maxMasters(); i++) {
271 accesses[access_idx].subname(i, system->getMasterName(i));
272 }
243 }
244
245 demandAccesses
246 .name(name() + ".demand_accesses")
247 .desc("number of demand (read+write) accesses")
273 }
274
275 demandAccesses
276 .name(name() + ".demand_accesses")
277 .desc("number of demand (read+write) accesses")
248 .flags(total)
278 .flags(total | nozero | nonan)
249 ;
250 demandAccesses = demandHits + demandMisses;
279 ;
280 demandAccesses = demandHits + demandMisses;
281 for (int i = 0; i < system->maxMasters(); i++) {
282 demandAccesses.subname(i, system->getMasterName(i));
283 }
251
252 overallAccesses
253 .name(name() + ".overall_accesses")
254 .desc("number of overall (read+write) accesses")
284
285 overallAccesses
286 .name(name() + ".overall_accesses")
287 .desc("number of overall (read+write) accesses")
255 .flags(total)
288 .flags(total | nozero | nonan)
256 ;
257 overallAccesses = overallHits + overallMisses;
289 ;
290 overallAccesses = overallHits + overallMisses;
291 for (int i = 0; i < system->maxMasters(); i++) {
292 overallAccesses.subname(i, system->getMasterName(i));
293 }
258
259 // miss rate formulas
260 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
261 MemCmd cmd(access_idx);
262 const string &cstr = cmd.toString();
263
264 missRate[access_idx]
265 .name(name() + "." + cstr + "_miss_rate")
266 .desc("miss rate for " + cstr + " accesses")
267 .flags(total | nozero | nonan)
268 ;
294
295 // miss rate formulas
296 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
297 MemCmd cmd(access_idx);
298 const string &cstr = cmd.toString();
299
300 missRate[access_idx]
301 .name(name() + "." + cstr + "_miss_rate")
302 .desc("miss rate for " + cstr + " accesses")
303 .flags(total | nozero | nonan)
304 ;
269
270 missRate[access_idx] = misses[access_idx] / accesses[access_idx];
305 missRate[access_idx] = misses[access_idx] / accesses[access_idx];
306
307 for (int i = 0; i < system->maxMasters(); i++) {
308 missRate[access_idx].subname(i, system->getMasterName(i));
309 }
271 }
272
273 demandMissRate
274 .name(name() + ".demand_miss_rate")
275 .desc("miss rate for demand accesses")
310 }
311
312 demandMissRate
313 .name(name() + ".demand_miss_rate")
314 .desc("miss rate for demand accesses")
276 .flags(total)
315 .flags(total | nozero | nonan)
277 ;
278 demandMissRate = demandMisses / demandAccesses;
316 ;
317 demandMissRate = demandMisses / demandAccesses;
318 for (int i = 0; i < system->maxMasters(); i++) {
319 demandMissRate.subname(i, system->getMasterName(i));
320 }
279
280 overallMissRate
281 .name(name() + ".overall_miss_rate")
282 .desc("miss rate for overall accesses")
321
322 overallMissRate
323 .name(name() + ".overall_miss_rate")
324 .desc("miss rate for overall accesses")
283 .flags(total)
325 .flags(total | nozero | nonan)
284 ;
285 overallMissRate = overallMisses / overallAccesses;
326 ;
327 overallMissRate = overallMisses / overallAccesses;
328 for (int i = 0; i < system->maxMasters(); i++) {
329 overallMissRate.subname(i, system->getMasterName(i));
330 }
286
287 // miss latency formulas
288 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
289 MemCmd cmd(access_idx);
290 const string &cstr = cmd.toString();
291
292 avgMissLatency[access_idx]
293 .name(name() + "." + cstr + "_avg_miss_latency")
294 .desc("average " + cstr + " miss latency")
295 .flags(total | nozero | nonan)
296 ;
331
332 // miss latency formulas
333 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
334 MemCmd cmd(access_idx);
335 const string &cstr = cmd.toString();
336
337 avgMissLatency[access_idx]
338 .name(name() + "." + cstr + "_avg_miss_latency")
339 .desc("average " + cstr + " miss latency")
340 .flags(total | nozero | nonan)
341 ;
297
298 avgMissLatency[access_idx] =
299 missLatency[access_idx] / misses[access_idx];
342 avgMissLatency[access_idx] =
343 missLatency[access_idx] / misses[access_idx];
344
345 for (int i = 0; i < system->maxMasters(); i++) {
346 avgMissLatency[access_idx].subname(i, system->getMasterName(i));
347 }
300 }
301
302 demandAvgMissLatency
303 .name(name() + ".demand_avg_miss_latency")
304 .desc("average overall miss latency")
348 }
349
350 demandAvgMissLatency
351 .name(name() + ".demand_avg_miss_latency")
352 .desc("average overall miss latency")
305 .flags(total)
353 .flags(total | nozero | nonan)
306 ;
307 demandAvgMissLatency = demandMissLatency / demandMisses;
354 ;
355 demandAvgMissLatency = demandMissLatency / demandMisses;
356 for (int i = 0; i < system->maxMasters(); i++) {
357 demandAvgMissLatency.subname(i, system->getMasterName(i));
358 }
308
309 overallAvgMissLatency
310 .name(name() + ".overall_avg_miss_latency")
311 .desc("average overall miss latency")
359
360 overallAvgMissLatency
361 .name(name() + ".overall_avg_miss_latency")
362 .desc("average overall miss latency")
312 .flags(total)
363 .flags(total | nozero | nonan)
313 ;
314 overallAvgMissLatency = overallMissLatency / overallMisses;
364 ;
365 overallAvgMissLatency = overallMissLatency / overallMisses;
366 for (int i = 0; i < system->maxMasters(); i++) {
367 overallAvgMissLatency.subname(i, system->getMasterName(i));
368 }
315
316 blocked_cycles.init(NUM_BLOCKED_CAUSES);
317 blocked_cycles
318 .name(name() + ".blocked_cycles")
319 .desc("number of cycles access was blocked")
320 .subname(Blocked_NoMSHRs, "no_mshrs")
321 .subname(Blocked_NoTargets, "no_targets")
322 ;

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345 ;
346
347 cacheCopies
348 .name(name() + ".cache_copies")
349 .desc("number of cache copies performed")
350 ;
351
352 writebacks
369
370 blocked_cycles.init(NUM_BLOCKED_CAUSES);
371 blocked_cycles
372 .name(name() + ".blocked_cycles")
373 .desc("number of cycles access was blocked")
374 .subname(Blocked_NoMSHRs, "no_mshrs")
375 .subname(Blocked_NoTargets, "no_targets")
376 ;

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399 ;
400
401 cacheCopies
402 .name(name() + ".cache_copies")
403 .desc("number of cache copies performed")
404 ;
405
406 writebacks
353 .init(maxThreadsPerCPU)
407 .init(system->maxMasters())
354 .name(name() + ".writebacks")
355 .desc("number of writebacks")
408 .name(name() + ".writebacks")
409 .desc("number of writebacks")
356 .flags(total)
410 .flags(total | nozero | nonan)
357 ;
411 ;
412 for (int i = 0; i < system->maxMasters(); i++) {
413 writebacks.subname(i, system->getMasterName(i));
414 }
358
359 // MSHR statistics
360 // MSHR hit statistics
361 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
362 MemCmd cmd(access_idx);
363 const string &cstr = cmd.toString();
364
365 mshr_hits[access_idx]
415
416 // MSHR statistics
417 // MSHR hit statistics
418 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
419 MemCmd cmd(access_idx);
420 const string &cstr = cmd.toString();
421
422 mshr_hits[access_idx]
366 .init(maxThreadsPerCPU)
423 .init(system->maxMasters())
367 .name(name() + "." + cstr + "_mshr_hits")
368 .desc("number of " + cstr + " MSHR hits")
369 .flags(total | nozero | nonan)
370 ;
424 .name(name() + "." + cstr + "_mshr_hits")
425 .desc("number of " + cstr + " MSHR hits")
426 .flags(total | nozero | nonan)
427 ;
428 for (int i = 0; i < system->maxMasters(); i++) {
429 mshr_hits[access_idx].subname(i, system->getMasterName(i));
430 }
371 }
372
373 demandMshrHits
374 .name(name() + ".demand_mshr_hits")
375 .desc("number of demand (read+write) MSHR hits")
431 }
432
433 demandMshrHits
434 .name(name() + ".demand_mshr_hits")
435 .desc("number of demand (read+write) MSHR hits")
376 .flags(total)
436 .flags(total | nozero | nonan)
377 ;
378 demandMshrHits = SUM_DEMAND(mshr_hits);
437 ;
438 demandMshrHits = SUM_DEMAND(mshr_hits);
439 for (int i = 0; i < system->maxMasters(); i++) {
440 demandMshrHits.subname(i, system->getMasterName(i));
441 }
379
380 overallMshrHits
381 .name(name() + ".overall_mshr_hits")
382 .desc("number of overall MSHR hits")
442
443 overallMshrHits
444 .name(name() + ".overall_mshr_hits")
445 .desc("number of overall MSHR hits")
383 .flags(total)
446 .flags(total | nozero | nonan)
384 ;
385 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
447 ;
448 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
449 for (int i = 0; i < system->maxMasters(); i++) {
450 overallMshrHits.subname(i, system->getMasterName(i));
451 }
386
387 // MSHR miss statistics
388 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
389 MemCmd cmd(access_idx);
390 const string &cstr = cmd.toString();
391
392 mshr_misses[access_idx]
452
453 // MSHR miss statistics
454 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
455 MemCmd cmd(access_idx);
456 const string &cstr = cmd.toString();
457
458 mshr_misses[access_idx]
393 .init(maxThreadsPerCPU)
459 .init(system->maxMasters())
394 .name(name() + "." + cstr + "_mshr_misses")
395 .desc("number of " + cstr + " MSHR misses")
396 .flags(total | nozero | nonan)
397 ;
460 .name(name() + "." + cstr + "_mshr_misses")
461 .desc("number of " + cstr + " MSHR misses")
462 .flags(total | nozero | nonan)
463 ;
464 for (int i = 0; i < system->maxMasters(); i++) {
465 mshr_misses[access_idx].subname(i, system->getMasterName(i));
466 }
398 }
399
400 demandMshrMisses
401 .name(name() + ".demand_mshr_misses")
402 .desc("number of demand (read+write) MSHR misses")
467 }
468
469 demandMshrMisses
470 .name(name() + ".demand_mshr_misses")
471 .desc("number of demand (read+write) MSHR misses")
403 .flags(total)
472 .flags(total | nozero | nonan)
404 ;
405 demandMshrMisses = SUM_DEMAND(mshr_misses);
473 ;
474 demandMshrMisses = SUM_DEMAND(mshr_misses);
475 for (int i = 0; i < system->maxMasters(); i++) {
476 demandMshrMisses.subname(i, system->getMasterName(i));
477 }
406
407 overallMshrMisses
408 .name(name() + ".overall_mshr_misses")
409 .desc("number of overall MSHR misses")
478
479 overallMshrMisses
480 .name(name() + ".overall_mshr_misses")
481 .desc("number of overall MSHR misses")
410 .flags(total)
482 .flags(total | nozero | nonan)
411 ;
412 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
483 ;
484 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
485 for (int i = 0; i < system->maxMasters(); i++) {
486 overallMshrMisses.subname(i, system->getMasterName(i));
487 }
413
414 // MSHR miss latency statistics
415 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
416 MemCmd cmd(access_idx);
417 const string &cstr = cmd.toString();
418
419 mshr_miss_latency[access_idx]
488
489 // MSHR miss latency statistics
490 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
491 MemCmd cmd(access_idx);
492 const string &cstr = cmd.toString();
493
494 mshr_miss_latency[access_idx]
420 .init(maxThreadsPerCPU)
495 .init(system->maxMasters())
421 .name(name() + "." + cstr + "_mshr_miss_latency")
422 .desc("number of " + cstr + " MSHR miss cycles")
423 .flags(total | nozero | nonan)
424 ;
496 .name(name() + "." + cstr + "_mshr_miss_latency")
497 .desc("number of " + cstr + " MSHR miss cycles")
498 .flags(total | nozero | nonan)
499 ;
500 for (int i = 0; i < system->maxMasters(); i++) {
501 mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
502 }
425 }
426
427 demandMshrMissLatency
428 .name(name() + ".demand_mshr_miss_latency")
429 .desc("number of demand (read+write) MSHR miss cycles")
503 }
504
505 demandMshrMissLatency
506 .name(name() + ".demand_mshr_miss_latency")
507 .desc("number of demand (read+write) MSHR miss cycles")
430 .flags(total)
508 .flags(total | nozero | nonan)
431 ;
432 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
509 ;
510 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
511 for (int i = 0; i < system->maxMasters(); i++) {
512 demandMshrMissLatency.subname(i, system->getMasterName(i));
513 }
433
434 overallMshrMissLatency
435 .name(name() + ".overall_mshr_miss_latency")
436 .desc("number of overall MSHR miss cycles")
514
515 overallMshrMissLatency
516 .name(name() + ".overall_mshr_miss_latency")
517 .desc("number of overall MSHR miss cycles")
437 .flags(total)
518 .flags(total | nozero | nonan)
438 ;
439 overallMshrMissLatency =
440 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
519 ;
520 overallMshrMissLatency =
521 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
522 for (int i = 0; i < system->maxMasters(); i++) {
523 overallMshrMissLatency.subname(i, system->getMasterName(i));
524 }
441
442 // MSHR uncacheable statistics
443 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
444 MemCmd cmd(access_idx);
445 const string &cstr = cmd.toString();
446
447 mshr_uncacheable[access_idx]
525
526 // MSHR uncacheable statistics
527 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
528 MemCmd cmd(access_idx);
529 const string &cstr = cmd.toString();
530
531 mshr_uncacheable[access_idx]
448 .init(maxThreadsPerCPU)
532 .init(system->maxMasters())
449 .name(name() + "." + cstr + "_mshr_uncacheable")
450 .desc("number of " + cstr + " MSHR uncacheable")
451 .flags(total | nozero | nonan)
452 ;
533 .name(name() + "." + cstr + "_mshr_uncacheable")
534 .desc("number of " + cstr + " MSHR uncacheable")
535 .flags(total | nozero | nonan)
536 ;
537 for (int i = 0; i < system->maxMasters(); i++) {
538 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
539 }
453 }
454
455 overallMshrUncacheable
456 .name(name() + ".overall_mshr_uncacheable_misses")
457 .desc("number of overall MSHR uncacheable misses")
540 }
541
542 overallMshrUncacheable
543 .name(name() + ".overall_mshr_uncacheable_misses")
544 .desc("number of overall MSHR uncacheable misses")
458 .flags(total)
545 .flags(total | nozero | nonan)
459 ;
460 overallMshrUncacheable =
461 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
546 ;
547 overallMshrUncacheable =
548 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
549 for (int i = 0; i < system->maxMasters(); i++) {
550 overallMshrUncacheable.subname(i, system->getMasterName(i));
551 }
462
463 // MSHR miss latency statistics
464 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
465 MemCmd cmd(access_idx);
466 const string &cstr = cmd.toString();
467
468 mshr_uncacheable_lat[access_idx]
552
553 // MSHR miss latency statistics
554 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
555 MemCmd cmd(access_idx);
556 const string &cstr = cmd.toString();
557
558 mshr_uncacheable_lat[access_idx]
469 .init(maxThreadsPerCPU)
559 .init(system->maxMasters())
470 .name(name() + "." + cstr + "_mshr_uncacheable_latency")
471 .desc("number of " + cstr + " MSHR uncacheable cycles")
472 .flags(total | nozero | nonan)
473 ;
560 .name(name() + "." + cstr + "_mshr_uncacheable_latency")
561 .desc("number of " + cstr + " MSHR uncacheable cycles")
562 .flags(total | nozero | nonan)
563 ;
564 for (int i = 0; i < system->maxMasters(); i++) {
565 mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i));
566 }
474 }
475
476 overallMshrUncacheableLatency
477 .name(name() + ".overall_mshr_uncacheable_latency")
478 .desc("number of overall MSHR uncacheable cycles")
567 }
568
569 overallMshrUncacheableLatency
570 .name(name() + ".overall_mshr_uncacheable_latency")
571 .desc("number of overall MSHR uncacheable cycles")
479 .flags(total)
572 .flags(total | nozero | nonan)
480 ;
481 overallMshrUncacheableLatency =
482 SUM_DEMAND(mshr_uncacheable_lat) +
483 SUM_NON_DEMAND(mshr_uncacheable_lat);
573 ;
574 overallMshrUncacheableLatency =
575 SUM_DEMAND(mshr_uncacheable_lat) +
576 SUM_NON_DEMAND(mshr_uncacheable_lat);
577 for (int i = 0; i < system->maxMasters(); i++) {
578 overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
579 }
484
485#if 0
486 // MSHR access formulas
487 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
488 MemCmd cmd(access_idx);
489 const string &cstr = cmd.toString();
490
491 mshrAccesses[access_idx]

--- 27 unchanged lines hidden (view full) ---

519 MemCmd cmd(access_idx);
520 const string &cstr = cmd.toString();
521
522 mshrMissRate[access_idx]
523 .name(name() + "." + cstr + "_mshr_miss_rate")
524 .desc("mshr miss rate for " + cstr + " accesses")
525 .flags(total | nozero | nonan)
526 ;
580
581#if 0
582 // MSHR access formulas
583 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
584 MemCmd cmd(access_idx);
585 const string &cstr = cmd.toString();
586
587 mshrAccesses[access_idx]

--- 27 unchanged lines hidden (view full) ---

615 MemCmd cmd(access_idx);
616 const string &cstr = cmd.toString();
617
618 mshrMissRate[access_idx]
619 .name(name() + "." + cstr + "_mshr_miss_rate")
620 .desc("mshr miss rate for " + cstr + " accesses")
621 .flags(total | nozero | nonan)
622 ;
527
528 mshrMissRate[access_idx] =
529 mshr_misses[access_idx] / accesses[access_idx];
623 mshrMissRate[access_idx] =
624 mshr_misses[access_idx] / accesses[access_idx];
625
626 for (int i = 0; i < system->maxMasters(); i++) {
627 mshrMissRate[access_idx].subname(i, system->getMasterName(i));
628 }
530 }
531
532 demandMshrMissRate
533 .name(name() + ".demand_mshr_miss_rate")
534 .desc("mshr miss rate for demand accesses")
629 }
630
631 demandMshrMissRate
632 .name(name() + ".demand_mshr_miss_rate")
633 .desc("mshr miss rate for demand accesses")
535 .flags(total)
634 .flags(total | nozero | nonan)
536 ;
537 demandMshrMissRate = demandMshrMisses / demandAccesses;
635 ;
636 demandMshrMissRate = demandMshrMisses / demandAccesses;
637 for (int i = 0; i < system->maxMasters(); i++) {
638 demandMshrMissRate.subname(i, system->getMasterName(i));
639 }
538
539 overallMshrMissRate
540 .name(name() + ".overall_mshr_miss_rate")
541 .desc("mshr miss rate for overall accesses")
640
641 overallMshrMissRate
642 .name(name() + ".overall_mshr_miss_rate")
643 .desc("mshr miss rate for overall accesses")
542 .flags(total)
644 .flags(total | nozero | nonan)
543 ;
544 overallMshrMissRate = overallMshrMisses / overallAccesses;
645 ;
646 overallMshrMissRate = overallMshrMisses / overallAccesses;
647 for (int i = 0; i < system->maxMasters(); i++) {
648 overallMshrMissRate.subname(i, system->getMasterName(i));
649 }
545
546 // mshrMiss latency formulas
547 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
548 MemCmd cmd(access_idx);
549 const string &cstr = cmd.toString();
550
551 avgMshrMissLatency[access_idx]
552 .name(name() + "." + cstr + "_avg_mshr_miss_latency")
553 .desc("average " + cstr + " mshr miss latency")
554 .flags(total | nozero | nonan)
555 ;
650
651 // mshrMiss latency formulas
652 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
653 MemCmd cmd(access_idx);
654 const string &cstr = cmd.toString();
655
656 avgMshrMissLatency[access_idx]
657 .name(name() + "." + cstr + "_avg_mshr_miss_latency")
658 .desc("average " + cstr + " mshr miss latency")
659 .flags(total | nozero | nonan)
660 ;
556
557 avgMshrMissLatency[access_idx] =
558 mshr_miss_latency[access_idx] / mshr_misses[access_idx];
661 avgMshrMissLatency[access_idx] =
662 mshr_miss_latency[access_idx] / mshr_misses[access_idx];
663
664 for (int i = 0; i < system->maxMasters(); i++) {
665 avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i));
666 }
559 }
560
561 demandAvgMshrMissLatency
562 .name(name() + ".demand_avg_mshr_miss_latency")
563 .desc("average overall mshr miss latency")
667 }
668
669 demandAvgMshrMissLatency
670 .name(name() + ".demand_avg_mshr_miss_latency")
671 .desc("average overall mshr miss latency")
564 .flags(total)
672 .flags(total | nozero | nonan)
565 ;
566 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
673 ;
674 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
675 for (int i = 0; i < system->maxMasters(); i++) {
676 demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
677 }
567
568 overallAvgMshrMissLatency
569 .name(name() + ".overall_avg_mshr_miss_latency")
570 .desc("average overall mshr miss latency")
678
679 overallAvgMshrMissLatency
680 .name(name() + ".overall_avg_mshr_miss_latency")
681 .desc("average overall mshr miss latency")
571 .flags(total)
682 .flags(total | nozero | nonan)
572 ;
573 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
683 ;
684 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
685 for (int i = 0; i < system->maxMasters(); i++) {
686 overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
687 }
574
575 // mshrUncacheable latency formulas
576 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
577 MemCmd cmd(access_idx);
578 const string &cstr = cmd.toString();
579
580 avgMshrUncacheableLatency[access_idx]
581 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
582 .desc("average " + cstr + " mshr uncacheable latency")
583 .flags(total | nozero | nonan)
584 ;
688
689 // mshrUncacheable latency formulas
690 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
691 MemCmd cmd(access_idx);
692 const string &cstr = cmd.toString();
693
694 avgMshrUncacheableLatency[access_idx]
695 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
696 .desc("average " + cstr + " mshr uncacheable latency")
697 .flags(total | nozero | nonan)
698 ;
585
586 avgMshrUncacheableLatency[access_idx] =
587 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
699 avgMshrUncacheableLatency[access_idx] =
700 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
701
702 for (int i = 0; i < system->maxMasters(); i++) {
703 avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i));
704 }
588 }
589
590 overallAvgMshrUncacheableLatency
591 .name(name() + ".overall_avg_mshr_uncacheable_latency")
592 .desc("average overall mshr uncacheable latency")
705 }
706
707 overallAvgMshrUncacheableLatency
708 .name(name() + ".overall_avg_mshr_uncacheable_latency")
709 .desc("average overall mshr uncacheable latency")
593 .flags(total)
710 .flags(total | nozero | nonan)
594 ;
595 overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable;
711 ;
712 overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable;
713 for (int i = 0; i < system->maxMasters(); i++) {
714 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
715 }
596
597 mshr_cap_events
716
717 mshr_cap_events
598 .init(maxThreadsPerCPU)
718 .init(system->maxMasters())
599 .name(name() + ".mshr_cap_events")
600 .desc("number of times MSHR cap was activated")
719 .name(name() + ".mshr_cap_events")
720 .desc("number of times MSHR cap was activated")
601 .flags(total)
721 .flags(total | nozero | nonan)
602 ;
722 ;
723 for (int i = 0; i < system->maxMasters(); i++) {
724 mshr_cap_events.subname(i, system->getMasterName(i));
725 }
603
604 //software prefetching stats
605 soft_prefetch_mshr_full
726
727 //software prefetching stats
728 soft_prefetch_mshr_full
606 .init(maxThreadsPerCPU)
729 .init(system->maxMasters())
607 .name(name() + ".soft_prefetch_mshr_full")
608 .desc("number of mshr full events for SW prefetching instrutions")
730 .name(name() + ".soft_prefetch_mshr_full")
731 .desc("number of mshr full events for SW prefetching instrutions")
609 .flags(total)
732 .flags(total | nozero | nonan)
610 ;
733 ;
734 for (int i = 0; i < system->maxMasters(); i++) {
735 soft_prefetch_mshr_full.subname(i, system->getMasterName(i));
736 }
611
612 mshr_no_allocate_misses
613 .name(name() +".no_allocate_misses")
614 .desc("Number of misses that were no-allocate")
615 ;
616
617}
618

--- 16 unchanged lines hidden --- 		737
738 mshr_no_allocate_misses
739 .name(name() +".no_allocate_misses")
740 .desc("Number of misses that were no-allocate")
741 ;
742
743}
744

--- 16 unchanged lines hidden ---