base.cc (8736:2d8a57343fe3) base.cc (8786:8be24baf68b8)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33 * Definition of BaseCache functions.
34 */
35
36#include "cpu/base.hh"
37#include "cpu/smt.hh"
38#include "debug/Cache.hh"
39#include "mem/cache/base.hh"
40#include "mem/cache/mshr.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33 * Definition of BaseCache functions.
34 */
35
36#include "cpu/base.hh"
37#include "cpu/smt.hh"
38#include "debug/Cache.hh"
39#include "mem/cache/base.hh"
40#include "mem/cache/mshr.hh"
41#include "sim/full_system.hh"
41
42using namespace std;
43
44BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
45 const std::string &_label)
46 : SimpleTimingPort(_name, _cache), cache(_cache),
42
43using namespace std;
44
45BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
46 const std::string &_label)
47 : SimpleTimingPort(_name, _cache), cache(_cache),
47 label(_label), blocked(false), mustSendRetry(false)
48 label(_label), otherPort(NULL),
49 blocked(false), mustSendRetry(false)
48{
49}
50
51
52BaseCache::BaseCache(const Params *p)
53 : MemObject(p),
54 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
55 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,

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63 noTargetMSHR(NULL),
64 missCount(p->max_miss_count),
65 drainEvent(NULL),
66 addrRange(p->addr_range),
67 _numCpus(p->num_cpus)
68{
69}
70
50{
51}
52
53
54BaseCache::BaseCache(const Params *p)
55 : MemObject(p),
56 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
57 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,

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65 noTargetMSHR(NULL),
66 missCount(p->max_miss_count),
67 drainEvent(NULL),
68 addrRange(p->addr_range),
69 _numCpus(p->num_cpus)
70{
71}
72
73void
74BaseCache::CachePort::recvStatusChange(Port::Status status)
75{
76 if (status == Port::RangeChange) {
77 otherPort->sendStatusChange(Port::RangeChange);
78 }
79}
71
80
81
72bool
73BaseCache::CachePort::checkFunctional(PacketPtr pkt)
74{
75 pkt->pushLabel(label);
76 bool done = SimpleTimingPort::checkFunctional(pkt);
77 pkt->popLabel();
78 return done;
79}

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112 DPRINTF(Cache, "Cache Unblocking\n");
113 blocked = false;
114 if (mustSendRetry)
115 {
116 DPRINTF(Cache, "Cache Sending Retry\n");
117 mustSendRetry = false;
118 SendRetryEvent *ev = new SendRetryEvent(this, true);
119 // @TODO: need to find a better time (next bus cycle?)
82bool
83BaseCache::CachePort::checkFunctional(PacketPtr pkt)
84{
85 pkt->pushLabel(label);
86 bool done = SimpleTimingPort::checkFunctional(pkt);
87 pkt->popLabel();
88 return done;
89}

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122 DPRINTF(Cache, "Cache Unblocking\n");
123 blocked = false;
124 if (mustSendRetry)
125 {
126 DPRINTF(Cache, "Cache Sending Retry\n");
127 mustSendRetry = false;
128 SendRetryEvent *ev = new SendRetryEvent(this, true);
129 // @TODO: need to find a better time (next bus cycle?)
120 cache->schedule(ev, curTick() + 1);
130 schedule(ev, curTick() + 1);
121 }
122}
123
124
125void
126BaseCache::init()
127{
128 if (!cpuSidePort || !memSidePort)
129 panic("Cache not hooked up on both sides\n");
131 }
132}
133
134
135void
136BaseCache::init()
137{
138 if (!cpuSidePort || !memSidePort)
139 panic("Cache not hooked up on both sides\n");
130 cpuSidePort->sendRangeChange();
140 cpuSidePort->sendStatusChange(Port::RangeChange);
131}
132
133
134void
135BaseCache::regStats()
136{
137 using namespace Stats;
138
139 // Hit statistics
140 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
141 MemCmd cmd(access_idx);
142 const string &cstr = cmd.toString();
143
144 hits[access_idx]
141}
142
143
144void
145BaseCache::regStats()
146{
147 using namespace Stats;
148
149 // Hit statistics
150 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
151 MemCmd cmd(access_idx);
152 const string &cstr = cmd.toString();
153
154 hits[access_idx]
145#if FULL_SYSTEM
146 .init(_numCpus + 1)
147#else
148 .init(_numCpus)
149#endif
155 .init(FullSystem ? (_numCpus + 1) : _numCpus)
150 .name(name() + "." + cstr + "_hits")
151 .desc("number of " + cstr + " hits")
152 .flags(total | nozero | nonan)
153 ;
154 }
155
156// These macros make it easier to sum the right subset of commands and
157// to change the subset of commands that are considered "demand" vs

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178 overallHits = demandHits + SUM_NON_DEMAND(hits);
179
180 // Miss statistics
181 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
182 MemCmd cmd(access_idx);
183 const string &cstr = cmd.toString();
184
185 misses[access_idx]
156 .name(name() + "." + cstr + "_hits")
157 .desc("number of " + cstr + " hits")
158 .flags(total | nozero | nonan)
159 ;
160 }
161
162// These macros make it easier to sum the right subset of commands and
163// to change the subset of commands that are considered "demand" vs

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184 overallHits = demandHits + SUM_NON_DEMAND(hits);
185
186 // Miss statistics
187 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
188 MemCmd cmd(access_idx);
189 const string &cstr = cmd.toString();
190
191 misses[access_idx]
186#if FULL_SYSTEM
187 .init(_numCpus + 1)
188#else
189 .init(_numCpus)
190#endif
192 .init(FullSystem ? (_numCpus + 1) : _numCpus)
191 .name(name() + "." + cstr + "_misses")
192 .desc("number of " + cstr + " misses")
193 .flags(total | nozero | nonan)
194 ;
195 }
196
197 demandMisses
198 .name(name() + ".demand_misses")

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194 .desc("number of " + cstr + " misses")
195 .flags(total | nozero | nonan)
196 ;
197 }
198
199 demandMisses
200 .name(name() + ".demand_misses")

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