base.cc (13866:d0829f20374a) base.cc (13892:0182a0601f66)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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72 : QueuedSlavePort(_name, _cache, queue),
73 queue(*_cache, *this, true, _label),
74 blocked(false), mustSendRetry(false),
75 sendRetryEvent([this]{ processSendRetry(); }, _name)
76{
77}
78
79BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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72 : QueuedSlavePort(_name, _cache, queue),
73 queue(*_cache, *this, true, _label),
74 blocked(false), mustSendRetry(false),
75 sendRetryEvent([this]{ processSendRetry(); }, _name)
76{
77}
78
79BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
80 : MemObject(p),
80 : ClockedObject(p),
81 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
82 memSidePort(p->name + ".mem_side", this, "MemSidePort"),
83 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
84 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
85 tags(p->tags),
86 prefetcher(p->prefetcher),
87 writeAllocator(p->write_allocator),
88 writebackClean(p->writeback_clean),

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188Port &
189BaseCache::getPort(const std::string &if_name, PortID idx)
190{
191 if (if_name == "mem_side") {
192 return memSidePort;
193 } else if (if_name == "cpu_side") {
194 return cpuSidePort;
195 } else {
81 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
82 memSidePort(p->name + ".mem_side", this, "MemSidePort"),
83 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
84 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
85 tags(p->tags),
86 prefetcher(p->prefetcher),
87 writeAllocator(p->write_allocator),
88 writebackClean(p->writeback_clean),

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188Port &
189BaseCache::getPort(const std::string &if_name, PortID idx)
190{
191 if (if_name == "mem_side") {
192 return memSidePort;
193 } else if (if_name == "cpu_side") {
194 return cpuSidePort;
195 } else {
196 return MemObject::getPort(if_name, idx);
196 return ClockedObject::getPort(if_name, idx);
197 }
198}
199
200bool
201BaseCache::inRange(Addr addr) const
202{
203 for (const auto& r : addrRanges) {
204 if (r.contains(addr)) {

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1691 "supported in the classic memory system. Please remove any "
1692 "caches or drain them properly before taking checkpoints.\n");
1693 }
1694}
1695
1696void
1697BaseCache::regStats()
1698{
197 }
198}
199
200bool
201BaseCache::inRange(Addr addr) const
202{
203 for (const auto& r : addrRanges) {
204 if (r.contains(addr)) {

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1691 "supported in the classic memory system. Please remove any "
1692 "caches or drain them properly before taking checkpoints.\n");
1693 }
1694}
1695
1696void
1697BaseCache::regStats()
1698{
1699 MemObject::regStats();
1699 ClockedObject::regStats();
1700
1701 using namespace Stats;
1702
1703 // Hit statistics
1704 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1705 MemCmd cmd(access_idx);
1706 const string &cstr = cmd.toString();
1707

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1701 using namespace Stats;
1702
1703 // Hit statistics
1704 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1705 MemCmd cmd(access_idx);
1706 const string &cstr = cmd.toString();
1707

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