base.cc (13784:1941dc118243) base.cc (13859:4156ac0c7257)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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434
435 if (mshr == noTargetMSHR) {
436 // we always clear at least one target
437 clearBlocked(Blocked_NoTargets);
438 noTargetMSHR = nullptr;
439 }
440
441 // Initial target is used just for stats
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 425 unchanged lines hidden (view full) ---

434
435 if (mshr == noTargetMSHR) {
436 // we always clear at least one target
437 clearBlocked(Blocked_NoTargets);
438 noTargetMSHR = nullptr;
439 }
440
441 // Initial target is used just for stats
442 MSHR::Target *initial_tgt = mshr->getTarget();
442 QueueEntry::Target *initial_tgt = mshr->getTarget();
443 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
444 Tick miss_latency = curTick() - initial_tgt->recvTime;
445
446 if (pkt->req->isUncacheable()) {
447 assert(pkt->req->masterId() < system->maxMasters());
448 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
449 miss_latency;
450 } else {

--- 2066 unchanged lines hidden --- 		443 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
444 Tick miss_latency = curTick() - initial_tgt->recvTime;
445
446 if (pkt->req->isUncacheable()) {
447 assert(pkt->req->masterId() < system->maxMasters());
448 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
449 miss_latency;
450 } else {

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