base.cc (13749:b2486662285d) base.cc (13750:11dd302dfaa4)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1284 // and a response that has data is the same in the end)
1285 if (pkt->isRead()) {
1286 // sanity checks
1287 assert(pkt->hasData());
1288 assert(pkt->getSize() == blkSize);
1289
1290 pkt->writeDataToBlock(blk->data, blkSize);
1291 }
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1275 unchanged lines hidden (view full) ---

1284 // and a response that has data is the same in the end)
1285 if (pkt->isRead()) {
1286 // sanity checks
1287 assert(pkt->hasData());
1288 assert(pkt->getSize() == blkSize);
1289
1290 pkt->writeDataToBlock(blk->data, blkSize);
1291 }
1292 // We pay for fillLatency here.
1293 blk->setWhenReady(clockEdge(fillLatency) + pkt->payloadDelay);
1292 // The block will be ready when the payload arrives and the fill is done
1293 blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
1294 pkt->payloadDelay);
1294
1295 return blk;
1296}
1297
1298CacheBlk*
1299BaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks)
1300{
1301 // Get address

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1296 return blk;
1297}
1298
1299CacheBlk*
1300BaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks)
1301{
1302 // Get address

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