base.cc (13478:59414c401cd9) base.cc (13564:9bbd53a77887)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64class BaseMasterPort;
65class BaseSlavePort;
66
67using namespace std;
68
69BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
70 BaseCache *_cache,
71 const std::string &_label)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64class BaseMasterPort;
65class BaseSlavePort;
66
67using namespace std;
68
69BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
70 BaseCache *_cache,
71 const std::string &_label)
72 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
72 : QueuedSlavePort(_name, _cache, queue),
73 queue(*_cache, *this, true, _label),
73 blocked(false), mustSendRetry(false),
74 sendRetryEvent([this]{ processSendRetry(); }, _name)
75{
76}
77
78BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
79 : MemObject(p),
80 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),

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223 // @todo: Make someone pay for this
224 pkt->headerDelay = pkt->payloadDelay = 0;
225
226 // In this case we are considering request_time that takes
227 // into account the delay of the xbar, if any, and just
228 // lat, neglecting responseLatency, modelling hit latency
229 // just as the value of lat overriden by access(), which calls
230 // the calculateAccessLatency() function.
74 blocked(false), mustSendRetry(false),
75 sendRetryEvent([this]{ processSendRetry(); }, _name)
76{
77}
78
79BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
80 : MemObject(p),
81 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),

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224 // @todo: Make someone pay for this
225 pkt->headerDelay = pkt->payloadDelay = 0;
226
227 // In this case we are considering request_time that takes
228 // into account the delay of the xbar, if any, and just
229 // lat, neglecting responseLatency, modelling hit latency
230 // just as the value of lat overriden by access(), which calls
231 // the calculateAccessLatency() function.
231 cpuSidePort.schedTimingResp(pkt, request_time, true);
232 cpuSidePort.schedTimingResp(pkt, request_time);
232 } else {
233 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
234 pkt->print());
235
236 // queue the packet for deletion, as the sending cache is
237 // still relying on it; if the block is found in access(),
238 // CleanEvict and Writeback messages will be deleted
239 // here as well

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395BaseCache::handleUncacheableWriteResp(PacketPtr pkt)
396{
397 Tick completion_time = clockEdge(responseLatency) +
398 pkt->headerDelay + pkt->payloadDelay;
399
400 // Reset the bus additional time as it is now accounted for
401 pkt->headerDelay = pkt->payloadDelay = 0;
402
233 } else {
234 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
235 pkt->print());
236
237 // queue the packet for deletion, as the sending cache is
238 // still relying on it; if the block is found in access(),
239 // CleanEvict and Writeback messages will be deleted
240 // here as well

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396BaseCache::handleUncacheableWriteResp(PacketPtr pkt)
397{
398 Tick completion_time = clockEdge(responseLatency) +
399 pkt->headerDelay + pkt->payloadDelay;
400
401 // Reset the bus additional time as it is now accounted for
402 pkt->headerDelay = pkt->payloadDelay = 0;
403
403 cpuSidePort.schedTimingResp(pkt, completion_time, true);
404 cpuSidePort.schedTimingResp(pkt, completion_time);
404}
405
406void
407BaseCache::recvTimingResp(PacketPtr pkt)
408{
409 assert(pkt->isResponse());
410
411 // all header delay should be paid for by the crossbar, unless

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2395 }
2396}
2397
2398BaseCache::MemSidePort::MemSidePort(const std::string &_name,
2399 BaseCache *_cache,
2400 const std::string &_label)
2401 : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2402 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
405}
406
407void
408BaseCache::recvTimingResp(PacketPtr pkt)
409{
410 assert(pkt->isResponse());
411
412 // all header delay should be paid for by the crossbar, unless

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2396 }
2397}
2398
2399BaseCache::MemSidePort::MemSidePort(const std::string &_name,
2400 BaseCache *_cache,
2401 const std::string &_label)
2402 : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2403 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2403 _snoopRespQueue(*_cache, *this, _label), cache(_cache)
2404 _snoopRespQueue(*_cache, *this, true, _label), cache(_cache)
2404{
2405}
2406
2407void
2408WriteAllocator::updateMode(Addr write_addr, unsigned write_size,
2409 Addr blk_addr)
2410{
2411 // check if we are continuing where the last write ended

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2406}
2407
2408void
2409WriteAllocator::updateMode(Addr write_addr, unsigned write_size,
2410 Addr blk_addr)
2411{
2412 // check if we are continuing where the last write ended

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