base.cc (13445:070fc4d948c0) base.cc (13477:044307c0d0b8)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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895 if (sequentialAccess) {
896 lat += dataLatency;
897 // Latency is dictated by the slowest of tag and data latencies
898 } else {
899 lat = std::max(lookup_lat, dataLatency);
900 }
901
902 // Check if the block to be accessed is available. If not, apply the
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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895 if (sequentialAccess) {
896 lat += dataLatency;
897 // Latency is dictated by the slowest of tag and data latencies
898 } else {
899 lat = std::max(lookup_lat, dataLatency);
900 }
901
902 // Check if the block to be accessed is available. If not, apply the
903 // access latency on top of block->whenReady.
904 if (blk->whenReady > curTick() &&
905 ticksToCycles(blk->whenReady - curTick()) > lat) {
906 lat += ticksToCycles(blk->whenReady - curTick());
903 // access latency on top of when the block is ready to be accessed.
904 const Tick when_ready = blk->getWhenReady();
905 if (when_ready > curTick() &&
906 ticksToCycles(when_ready - curTick()) > lat) {
907 lat += ticksToCycles(when_ready - curTick());
907 }
908 }
909
910 return lat;
911}
912
913bool
914BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,

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1019 blk->status |= BlkWritable;
1020 }
1021 // nothing else to do; writeback doesn't expect response
1022 assert(!pkt->needsResponse());
1023 pkt->writeDataToBlock(blk->data, blkSize);
1024 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1025 incHitCount(pkt);
1026 // populate the time when the block will be ready to access.
908 }
909 }
910
911 return lat;
912}
913
914bool
915BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,

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1020 blk->status |= BlkWritable;
1021 }
1022 // nothing else to do; writeback doesn't expect response
1023 assert(!pkt->needsResponse());
1024 pkt->writeDataToBlock(blk->data, blkSize);
1025 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1026 incHitCount(pkt);
1027 // populate the time when the block will be ready to access.
1027 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1028 pkt->payloadDelay;
1028 blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
1029 pkt->payloadDelay);
1029 return true;
1030 } else if (pkt->cmd == MemCmd::CleanEvict) {
1031 if (blk) {
1032 // Found the block in the tags, need to stop CleanEvict from
1033 // propagating further down the hierarchy. Returning true will
1034 // treat the CleanEvict like a satisfied write request and delete
1035 // it.
1036 return true;

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1076 }
1077 // nothing else to do; writeback doesn't expect response
1078 assert(!pkt->needsResponse());
1079 pkt->writeDataToBlock(blk->data, blkSize);
1080 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1081
1082 incHitCount(pkt);
1083 // populate the time when the block will be ready to access.
1030 return true;
1031 } else if (pkt->cmd == MemCmd::CleanEvict) {
1032 if (blk) {
1033 // Found the block in the tags, need to stop CleanEvict from
1034 // propagating further down the hierarchy. Returning true will
1035 // treat the CleanEvict like a satisfied write request and delete
1036 // it.
1037 return true;

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1077 }
1078 // nothing else to do; writeback doesn't expect response
1079 assert(!pkt->needsResponse());
1080 pkt->writeDataToBlock(blk->data, blkSize);
1081 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1082
1083 incHitCount(pkt);
1084 // populate the time when the block will be ready to access.
1084 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1085 pkt->payloadDelay;
1085 blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
1086 pkt->payloadDelay);
1086 // if this a write-through packet it will be sent to cache
1087 // below
1088 return !pkt->writeThrough();
1089 } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
1090 blk->isReadable())) {
1091 // OK to satisfy access
1092 incHitCount(pkt);
1093 satisfyRequest(pkt, blk);

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1207 if (pkt->isRead()) {
1208 // sanity checks
1209 assert(pkt->hasData());
1210 assert(pkt->getSize() == blkSize);
1211
1212 pkt->writeDataToBlock(blk->data, blkSize);
1213 }
1214 // We pay for fillLatency here.
1087 // if this a write-through packet it will be sent to cache
1088 // below
1089 return !pkt->writeThrough();
1090 } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
1091 blk->isReadable())) {
1092 // OK to satisfy access
1093 incHitCount(pkt);
1094 satisfyRequest(pkt, blk);

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1208 if (pkt->isRead()) {
1209 // sanity checks
1210 assert(pkt->hasData());
1211 assert(pkt->getSize() == blkSize);
1212
1213 pkt->writeDataToBlock(blk->data, blkSize);
1214 }
1215 // We pay for fillLatency here.
1215 blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
1216 pkt->payloadDelay;
1216 blk->setWhenReady(clockEdge(fillLatency) + pkt->payloadDelay);
1217
1218 return blk;
1219}
1220
1221CacheBlk*
1222BaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks)
1223{
1224 // Get address

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1218 return blk;
1219}
1220
1221CacheBlk*
1222BaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks)
1223{
1224 // Get address

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