base.cc (13416:d90887d0c889) base.cc (13418:08101e89101e)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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90 name(), false,
91 EventBase::Delayed_Writeback_Pri),
92 blkSize(blk_size),
93 lookupLatency(p->tag_latency),
94 dataLatency(p->data_latency),
95 forwardLatency(p->tag_latency),
96 fillLatency(p->data_latency),
97 responseLatency(p->response_latency),
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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90 name(), false,
91 EventBase::Delayed_Writeback_Pri),
92 blkSize(blk_size),
93 lookupLatency(p->tag_latency),
94 dataLatency(p->data_latency),
95 forwardLatency(p->tag_latency),
96 fillLatency(p->data_latency),
97 responseLatency(p->response_latency),
98 sequentialAccess(p->sequential_access),
98 numTarget(p->tgts_per_mshr),
99 forwardSnoops(true),
100 clusivity(p->clusivity),
101 isReadOnly(p->is_read_only),
102 blocked(0),
103 order(0),
104 noTargetMSHR(nullptr),
105 missCount(p->max_miss_count),

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220 if (pkt->needsResponse()) {
221 pkt->makeTimingResponse();
222 // @todo: Make someone pay for this
223 pkt->headerDelay = pkt->payloadDelay = 0;
224
225 // In this case we are considering request_time that takes
226 // into account the delay of the xbar, if any, and just
227 // lat, neglecting responseLatency, modelling hit latency
99 numTarget(p->tgts_per_mshr),
100 forwardSnoops(true),
101 clusivity(p->clusivity),
102 isReadOnly(p->is_read_only),
103 blocked(0),
104 order(0),
105 noTargetMSHR(nullptr),
106 missCount(p->max_miss_count),

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221 if (pkt->needsResponse()) {
222 pkt->makeTimingResponse();
223 // @todo: Make someone pay for this
224 pkt->headerDelay = pkt->payloadDelay = 0;
225
226 // In this case we are considering request_time that takes
227 // into account the delay of the xbar, if any, and just
228 // lat, neglecting responseLatency, modelling hit latency
228 // just as lookupLatency or or the value of lat overriden
229 // by access(), that calls accessBlock() function.
229 // just as the value of lat overriden by access(), which calls
230 // the calculateAccessLatency() function.
230 cpuSidePort.schedTimingResp(pkt, request_time, true);
231 } else {
232 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
233 pkt->print());
234
235 // queue the packet for deletion, as the sending cache is
236 // still relying on it; if the block is found in access(),
237 // CleanEvict and Writeback messages will be deleted

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337
338void
339BaseCache::recvTimingReq(PacketPtr pkt)
340{
341 // anything that is merely forwarded pays for the forward latency and
342 // the delay provided by the crossbar
343 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
344
231 cpuSidePort.schedTimingResp(pkt, request_time, true);
232 } else {
233 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
234 pkt->print());
235
236 // queue the packet for deletion, as the sending cache is
237 // still relying on it; if the block is found in access(),
238 // CleanEvict and Writeback messages will be deleted

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338
339void
340BaseCache::recvTimingReq(PacketPtr pkt)
341{
342 // anything that is merely forwarded pays for the forward latency and
343 // the delay provided by the crossbar
344 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
345
345 // We use lookupLatency here because it is used to specify the latency
346 // to access.
347 Cycles lat = lookupLatency;
346 Cycles lat;
348 CacheBlk *blk = nullptr;
349 bool satisfied = false;
350 {
351 PacketList writebacks;
352 // Note that lat is passed by reference here. The function
347 CacheBlk *blk = nullptr;
348 bool satisfied = false;
349 {
350 PacketList writebacks;
351 // Note that lat is passed by reference here. The function
353 // access() calls accessBlock() which can modify lat value.
352 // access() will set the lat value.
354 satisfied = access(pkt, blk, lat, writebacks);
355
356 // copy writebacks to write buffer here to ensure they logically
357 // precede anything happening below
358 doWritebacks(writebacks, forward_time);
359 }
360
361 // Here we charge the headerDelay that takes into account the latencies
362 // of the bus, if the packet comes from it.
353 satisfied = access(pkt, blk, lat, writebacks);
354
355 // copy writebacks to write buffer here to ensure they logically
356 // precede anything happening below
357 doWritebacks(writebacks, forward_time);
358 }
359
360 // Here we charge the headerDelay that takes into account the latencies
361 // of the bus, if the packet comes from it.
363 // The latency charged it is just lat that is the value of lookupLatency
364 // modified by access() function, or if not just lookupLatency.
362 // The latency charged is just the value set by the access() function.
365 // In case of a hit we are neglecting response latency.
366 // In case of a miss we are neglecting forward latency.
367 Tick request_time = clockEdge(lat) + pkt->headerDelay;
368 // Here we reset the timing of the packet.
369 pkt->headerDelay = pkt->payloadDelay = 0;
370
371 if (satisfied) {
372 // notify before anything else as later handleTimingReqHit might turn

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881 }
882}
883
884/////////////////////////////////////////////////////
885//
886// Access path: requests coming in from the CPU side
887//
888/////////////////////////////////////////////////////
363 // In case of a hit we are neglecting response latency.
364 // In case of a miss we are neglecting forward latency.
365 Tick request_time = clockEdge(lat) + pkt->headerDelay;
366 // Here we reset the timing of the packet.
367 pkt->headerDelay = pkt->payloadDelay = 0;
368
369 if (satisfied) {
370 // notify before anything else as later handleTimingReqHit might turn

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879 }
880}
881
882/////////////////////////////////////////////////////
883//
884// Access path: requests coming in from the CPU side
885//
886/////////////////////////////////////////////////////
887Cycles
888BaseCache::calculateAccessLatency(const CacheBlk* blk,
889 const Cycles lookup_lat) const
890{
891 Cycles lat(lookup_lat);
889
892
893 if (blk != nullptr) {
894 // First access tags, then data
895 if (sequentialAccess) {
896 lat += dataLatency;
897 // Latency is dictated by the slowest of tag and data latencies
898 } else {
899 lat = std::max(lookup_lat, dataLatency);
900 }
901
902 // Check if the block to be accessed is available. If not, apply the
903 // access latency on top of block->whenReady.
904 if (blk->whenReady > curTick() &&
905 ticksToCycles(blk->whenReady - curTick()) > lat) {
906 lat += ticksToCycles(blk->whenReady - curTick());
907 }
908 }
909
910 return lat;
911}
912
890bool
891BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
892 PacketList &writebacks)
893{
894 // sanity check
895 assert(pkt->isRequest());
896
897 chatty_assert(!(isReadOnly && pkt->isWrite()),
898 "Should never see a write in a read-only cache %s\n",
899 name());
900
913bool
914BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
915 PacketList &writebacks)
916{
917 // sanity check
918 assert(pkt->isRequest());
919
920 chatty_assert(!(isReadOnly && pkt->isWrite()),
921 "Should never see a write in a read-only cache %s\n",
922 name());
923
901 // Here lat is the value passed as parameter to accessBlock() function
902 // that can modify its value.
903 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
924 // Access block in the tags
925 Cycles tag_latency(0);
926 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency);
904
927
928 // Calculate access latency
929 lat = calculateAccessLatency(blk, tag_latency);
930
905 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
906 blk ? "hit " + blk->print() : "miss");
907
908 if (pkt->req->isCacheMaintenance()) {
909 // A cache maintenance operation is always forwarded to the
910 // memory below even if the block is found in dirty state.
911
912 // We defer any changes to the state of the block until we

--- 1510 unchanged lines hidden --- 		931 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
932 blk ? "hit " + blk->print() : "miss");
933
934 if (pkt->req->isCacheMaintenance()) {
935 // A cache maintenance operation is always forwarded to the
936 // memory below even if the block is found in dirty state.
937
938 // We defer any changes to the state of the block until we

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