base.cc (13412:bc5b08f44e6d) base.cc (13416:d90887d0c889)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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78BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
79 : MemObject(p),
80 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
81 memSidePort(p->name + ".mem_side", this, "MemSidePort"),
82 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
83 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
84 tags(p->tags),
85 prefetcher(p->prefetcher),
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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78BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
79 : MemObject(p),
80 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
81 memSidePort(p->name + ".mem_side", this, "MemSidePort"),
82 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
83 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
84 tags(p->tags),
85 prefetcher(p->prefetcher),
86 prefetchOnAccess(p->prefetch_on_access),
87 writeAllocator(p->write_allocator),
88 writebackClean(p->writeback_clean),
89 tempBlockWriteback(nullptr),
90 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
91 name(), false,
92 EventBase::Delayed_Writeback_Pri),
93 blkSize(blk_size),
94 lookupLatency(p->tag_latency),

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363 // of the bus, if the packet comes from it.
364 // The latency charged it is just lat that is the value of lookupLatency
365 // modified by access() function, or if not just lookupLatency.
366 // In case of a hit we are neglecting response latency.
367 // In case of a miss we are neglecting forward latency.
368 Tick request_time = clockEdge(lat) + pkt->headerDelay;
369 // Here we reset the timing of the packet.
370 pkt->headerDelay = pkt->payloadDelay = 0;
86 writeAllocator(p->write_allocator),
87 writebackClean(p->writeback_clean),
88 tempBlockWriteback(nullptr),
89 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
90 name(), false,
91 EventBase::Delayed_Writeback_Pri),
92 blkSize(blk_size),
93 lookupLatency(p->tag_latency),

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362 // of the bus, if the packet comes from it.
363 // The latency charged it is just lat that is the value of lookupLatency
364 // modified by access() function, or if not just lookupLatency.
365 // In case of a hit we are neglecting response latency.
366 // In case of a miss we are neglecting forward latency.
367 Tick request_time = clockEdge(lat) + pkt->headerDelay;
368 // Here we reset the timing of the packet.
369 pkt->headerDelay = pkt->payloadDelay = 0;
371 // track time of availability of next prefetch, if any
372 Tick next_pf_time = MaxTick;
373
374 if (satisfied) {
370
371 if (satisfied) {
375 // if need to notify the prefetcher we have to do it before
376 // anything else as later handleTimingReqHit might turn the
377 // packet in a response
378 if (prefetcher &&
379 (prefetchOnAccess || (blk && blk->wasPrefetched()))) {
380 if (blk)
381 blk->status &= ~BlkHWPrefetched;
372 // notify before anything else as later handleTimingReqHit might turn
373 // the packet in a response
374 ppHit->notify(pkt);
382
375
383 // Don't notify on SWPrefetch
384 if (!pkt->cmd.isSWPrefetch()) {
385 assert(!pkt->req->isCacheMaintenance());
386 next_pf_time = prefetcher->notify(pkt);
387 }
376 if (prefetcher && blk && blk->wasPrefetched()) {
377 blk->status &= ~BlkHWPrefetched;
388 }
389
390 handleTimingReqHit(pkt, blk, request_time);
391 } else {
392 handleTimingReqMiss(pkt, blk, forward_time, request_time);
393
378 }
379
380 handleTimingReqHit(pkt, blk, request_time);
381 } else {
382 handleTimingReqMiss(pkt, blk, forward_time, request_time);
383
394 // We should call the prefetcher reguardless if the request is
395 // satisfied or not, reguardless if the request is in the MSHR
396 // or not. The request could be a ReadReq hit, but still not
397 // satisfied (potentially because of a prior write to the same
398 // cache line. So, even when not satisfied, there is an MSHR
399 // already allocated for this, we need to let the prefetcher
400 // know about the request
384 ppMiss->notify(pkt);
385 }
401
386
402 // Don't notify prefetcher on SWPrefetch, cache maintenance
403 // operations or for writes that we are coaslescing.
404 if (prefetcher && pkt &&
405 !pkt->cmd.isSWPrefetch() &&
406 !pkt->req->isCacheMaintenance() &&
407 !(writeAllocator && writeAllocator->coalesce() &&
408 pkt->isWrite())) {
409 next_pf_time = prefetcher->notify(pkt);
387 if (prefetcher) {
388 // track time of availability of next prefetch, if any
389 Tick next_pf_time = prefetcher->nextPrefetchReadyTime();
390 if (next_pf_time != MaxTick) {
391 schedMemSideSendEvent(next_pf_time);
410 }
411 }
392 }
393 }
412
413 if (next_pf_time != MaxTick) {
414 schedMemSideSendEvent(next_pf_time);
415 }
416}
417
418void
419BaseCache::handleUncacheableWriteResp(PacketPtr pkt)
420{
421 Tick completion_time = clockEdge(responseLatency) +
422 pkt->headerDelay + pkt->payloadDelay;
423

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1402}
1403
1404bool
1405BaseCache::isDirty() const
1406{
1407 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); });
1408}
1409
394}
395
396void
397BaseCache::handleUncacheableWriteResp(PacketPtr pkt)
398{
399 Tick completion_time = clockEdge(responseLatency) +
400 pkt->headerDelay + pkt->payloadDelay;
401

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1380}
1381
1382bool
1383BaseCache::isDirty() const
1384{
1385 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); });
1386}
1387
1388bool
1389BaseCache::coalesce() const
1390{
1391 return writeAllocator && writeAllocator->coalesce();
1392}
1393
1410void
1411BaseCache::writebackVisitor(CacheBlk &blk)
1412{
1413 if (blk.isDirty()) {
1414 assert(blk.isValid());
1415
1416 RequestPtr request = std::make_shared<Request>(
1417 regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId);

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2205 }
2206
2207 replacements
2208 .name(name() + ".replacements")
2209 .desc("number of replacements")
2210 ;
2211}
2212
1394void
1395BaseCache::writebackVisitor(CacheBlk &blk)
1396{
1397 if (blk.isDirty()) {
1398 assert(blk.isValid());
1399
1400 RequestPtr request = std::make_shared<Request>(
1401 regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId);

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2189 }
2190
2191 replacements
2192 .name(name() + ".replacements")
2193 .desc("number of replacements")
2194 ;
2195}
2196
2197void
2198BaseCache::regProbePoints()
2199{
2200 ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit");
2201 ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss");
2202}
2203
2213///////////////
2214//
2215// CpuSidePort
2216//
2217///////////////
2218bool
2219BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2220{

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2205//
2206// CpuSidePort
2207//
2208///////////////
2209bool
2210BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2211{

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