base.cc (13378:038ea95fd793) base.cc (13412:bc5b08f44e6d)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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564 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
565 delete pkt;
566}
567
568
569Tick
570BaseCache::recvAtomic(PacketPtr pkt)
571{
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 555 unchanged lines hidden (view full) ---

564 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
565 delete pkt;
566}
567
568
569Tick
570BaseCache::recvAtomic(PacketPtr pkt)
571{
572 // We are in atomic mode so we pay just for lookupLatency here.
573 Cycles lat = lookupLatency;
574
575 // follow the same flow as in recvTimingReq, and check if a cache
576 // above us is responding
577 if (pkt->cacheResponding() && !pkt->isClean()) {
578 assert(!pkt->req->isCacheInvalidate());
579 DPRINTF(Cache, "Cache above responding to %s: not responding\n",
580 pkt->print());
581
582 // if a cache is responding, and it had the line in Owned
583 // rather than Modified state, we need to invalidate any
584 // copies that are not on the same path to memory
585 assert(pkt->needsWritable() && !pkt->responderHadWritable());
586 lat += ticksToCycles(memSidePort.sendAtomic(pkt));
587
588 return lat * clockPeriod();
589 }
590
591 // should assert here that there are no outstanding MSHRs or
592 // writebacks... that would mean that someone used an atomic
593 // access in timing mode
594
572 // should assert here that there are no outstanding MSHRs or
573 // writebacks... that would mean that someone used an atomic
574 // access in timing mode
575
576 // We use lookupLatency here because it is used to specify the latency
577 // to access.
578 Cycles lat = lookupLatency;
579
595 CacheBlk *blk = nullptr;
596 PacketList writebacks;
597 bool satisfied = access(pkt, blk, lat, writebacks);
598
599 if (pkt->isClean() && blk && blk->isDirty()) {
600 // A cache clean opearation is looking for a dirty
601 // block. If a dirty block is encountered a WriteClean
602 // will update any copies to the path to the memory

--- 1844 unchanged lines hidden --- 		580 CacheBlk *blk = nullptr;
581 PacketList writebacks;
582 bool satisfied = access(pkt, blk, lat, writebacks);
583
584 if (pkt->isClean() && blk && blk->isDirty()) {
585 // A cache clean opearation is looking for a dirty
586 // block. If a dirty block is encountered a WriteClean
587 // will update any copies to the path to the memory

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