base.cc (12724:4f6fac3191d2) base.cc (12725:3dcb96899659)
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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627 }
628
629 return lat * clockPeriod();
630}
631
632void
633BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
634{
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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627 }
628
629 return lat * clockPeriod();
630}
631
632void
633BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
634{
635 if (system->bypassCaches()) {
636 // Packets from the memory side are snoop request and
637 // shouldn't happen in bypass mode.
638 assert(from_cpu_side);
639
640 // The cache should be flushed if we are in cache bypass mode,
641 // so we don't need to check if we need to update anything.
642 memSidePort.sendFunctional(pkt);
643 return;
644 }
645
646 Addr blk_addr = pkt->getBlockAddr(blkSize);
647 bool is_secure = pkt->isSecure();
648 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
649 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
650
651 pkt->pushLabel(name());
652
653 CacheBlkPrintWrapper cbpw(blk);

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2142///////////////
2143//
2144// CpuSidePort
2145//
2146///////////////
2147bool
2148BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2149{
635 Addr blk_addr = pkt->getBlockAddr(blkSize);
636 bool is_secure = pkt->isSecure();
637 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
638 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
639
640 pkt->pushLabel(name());
641
642 CacheBlkPrintWrapper cbpw(blk);

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2131///////////////
2132//
2133// CpuSidePort
2134//
2135///////////////
2136bool
2137BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2138{
2139 // Snoops shouldn't happen when bypassing caches
2140 assert(!cache->system->bypassCaches());
2141
2142 assert(pkt->isResponse());
2143
2150 // Express snoop responses from master to slave, e.g., from L1 to L2
2151 cache->recvTimingSnoopResp(pkt);
2152 return true;
2153}
2154
2155
2156bool
2157BaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
2158{
2144 // Express snoop responses from master to slave, e.g., from L1 to L2
2145 cache->recvTimingSnoopResp(pkt);
2146 return true;
2147}
2148
2149
2150bool
2151BaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
2152{
2159 if (pkt->isExpressSnoop()) {
2153 if (cache->system->bypassCaches() || pkt->isExpressSnoop()) {
2160 // always let express snoop packets through even if blocked
2161 return true;
2162 } else if (blocked || mustSendRetry) {
2163 // either already committed to send a retry, or blocked
2164 mustSendRetry = true;
2165 return false;
2166 }
2167 mustSendRetry = false;
2168 return true;
2169}
2170
2171bool
2172BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2173{
2154 // always let express snoop packets through even if blocked
2155 return true;
2156 } else if (blocked || mustSendRetry) {
2157 // either already committed to send a retry, or blocked
2158 mustSendRetry = true;
2159 return false;
2160 }
2161 mustSendRetry = false;
2162 return true;
2163}
2164
2165bool
2166BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2167{
2174 if (tryTiming(pkt)) {
2168 assert(pkt->isRequest());
2169
2170 if (cache->system->bypassCaches()) {
2171 // Just forward the packet if caches are disabled.
2172 // @todo This should really enqueue the packet rather
2173 bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt);
2174 assert(success);
2175 return true;
2176 } else if (tryTiming(pkt)) {
2175 cache->recvTimingReq(pkt);
2176 return true;
2177 }
2178 return false;
2179}
2180
2181Tick
2182BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
2183{
2177 cache->recvTimingReq(pkt);
2178 return true;
2179 }
2180 return false;
2181}
2182
2183Tick
2184BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
2185{
2184 return cache->recvAtomic(pkt);
2186 if (cache->system->bypassCaches()) {
2187 // Forward the request if the system is in cache bypass mode.
2188 return cache->memSidePort.sendAtomic(pkt);
2189 } else {
2190 return cache->recvAtomic(pkt);
2191 }
2185}
2186
2187void
2188BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
2189{
2192}
2193
2194void
2195BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
2196{
2197 if (cache->system->bypassCaches()) {
2198 // The cache should be flushed if we are in cache bypass mode,
2199 // so we don't need to check if we need to update anything.
2200 cache->memSidePort.sendFunctional(pkt);
2201 return;
2202 }
2203
2190 // functional request
2191 cache->functionalAccess(pkt, true);
2192}
2193
2194AddrRangeList
2195BaseCache::CpuSidePort::getAddrRanges() const
2196{
2197 return cache->getAddrRanges();

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2216 cache->recvTimingResp(pkt);
2217 return true;
2218}
2219
2220// Express snooping requests to memside port
2221void
2222BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2223{
2204 // functional request
2205 cache->functionalAccess(pkt, true);
2206}
2207
2208AddrRangeList
2209BaseCache::CpuSidePort::getAddrRanges() const
2210{
2211 return cache->getAddrRanges();

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2230 cache->recvTimingResp(pkt);
2231 return true;
2232}
2233
2234// Express snooping requests to memside port
2235void
2236BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2237{
2238 // Snoops shouldn't happen when bypassing caches
2239 assert(!cache->system->bypassCaches());
2240
2224 // handle snooping requests
2225 cache->recvTimingSnoopReq(pkt);
2226}
2227
2228Tick
2229BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2230{
2241 // handle snooping requests
2242 cache->recvTimingSnoopReq(pkt);
2243}
2244
2245Tick
2246BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2247{
2248 // Snoops shouldn't happen when bypassing caches
2249 assert(!cache->system->bypassCaches());
2250
2231 return cache->recvAtomicSnoop(pkt);
2232}
2233
2234void
2235BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2236{
2251 return cache->recvAtomicSnoop(pkt);
2252}
2253
2254void
2255BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2256{
2257 // Snoops shouldn't happen when bypassing caches
2258 assert(!cache->system->bypassCaches());
2259
2237 // functional snoop (note that in contrast to atomic we don't have
2238 // a specific functionalSnoop method, as they have the same
2239 // behaviour regardless)
2240 cache->functionalAccess(pkt, false);
2241}
2242
2243void
2244BaseCache::CacheReqPacketQueue::sendDeferredPacket()

--- 42 unchanged lines hidden --- 		2260 // functional snoop (note that in contrast to atomic we don't have
2261 // a specific functionalSnoop method, as they have the same
2262 // behaviour regardless)
2263 cache->functionalAccess(pkt, false);
2264}
2265
2266void
2267BaseCache::CacheReqPacketQueue::sendDeferredPacket()

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