base.cc (11053:62544e45c0f4) base.cc (11331:cd5c48db28e6)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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72 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0,
73 MSHRQueue_WriteBuffer),
74 blkSize(blk_size),
75 lookupLatency(p->hit_latency),
76 forwardLatency(p->hit_latency),
77 fillLatency(p->response_latency),
78 responseLatency(p->response_latency),
79 numTarget(p->tgts_per_mshr),
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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72 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0,
73 MSHRQueue_WriteBuffer),
74 blkSize(blk_size),
75 lookupLatency(p->hit_latency),
76 forwardLatency(p->hit_latency),
77 fillLatency(p->response_latency),
78 responseLatency(p->response_latency),
79 numTarget(p->tgts_per_mshr),
80 forwardSnoops(p->forward_snoops),
80 forwardSnoops(true),
81 isReadOnly(p->is_read_only),
82 blocked(0),
83 order(0),
84 noTargetMSHR(NULL),
85 missCount(p->max_miss_count),
86 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
87 system(p->system)
88{
81 isReadOnly(p->is_read_only),
82 blocked(0),
83 order(0),
84 noTargetMSHR(NULL),
85 missCount(p->max_miss_count),
86 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
87 system(p->system)
88{
89 // forward snoops is overridden in init() once we can query
90 // whether the connected master is actually snooping or not
89}
90
91void
92BaseCache::CacheSlavePort::setBlocked()
93{
94 assert(!blocked);
95 DPRINTF(CachePort, "Port is blocking new requests\n");
96 blocked = true;

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126}
127
128void
129BaseCache::init()
130{
131 if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
132 fatal("Cache ports on %s are not connected\n", name());
133 cpuSidePort->sendRangeChange();
91}
92
93void
94BaseCache::CacheSlavePort::setBlocked()
95{
96 assert(!blocked);
97 DPRINTF(CachePort, "Port is blocking new requests\n");
98 blocked = true;

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128}
129
130void
131BaseCache::init()
132{
133 if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
134 fatal("Cache ports on %s are not connected\n", name());
135 cpuSidePort->sendRangeChange();
136 forwardSnoops = cpuSidePort->isSnooping();
134}
135
136BaseMasterPort &
137BaseCache::getMasterPort(const std::string &if_name, PortID idx)
138{
139 if (if_name == "mem_side") {
140 return *memSidePort;
141 } else {

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138
139BaseMasterPort &
140BaseCache::getMasterPort(const std::string &if_name, PortID idx)
141{
142 if (if_name == "mem_side") {
143 return *memSidePort;
144 } else {

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