base.cc (10910:32f3d1c454ec) | base.cc (10912:b99a6662d7c2) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 761 unchanged lines hidden (view full) --- 770 771 mshr_no_allocate_misses 772 .name(name() +".no_allocate_misses") 773 .desc("Number of misses that were no-allocate") 774 ; 775 776} 777 | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 761 unchanged lines hidden (view full) --- 770 771 mshr_no_allocate_misses 772 .name(name() +".no_allocate_misses") 773 .desc("Number of misses that were no-allocate") 774 ; 775 776} 777 |
778unsigned int 779BaseCache::drain(DrainManager *dm) 780{ 781 int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) + 782 mshrQueue.drain(dm) + writeBuffer.drain(dm); 783 784 // Set status 785 if (count != 0) { 786 setDrainState(DrainState::Draining); 787 DPRINTF(Drain, "Cache not drained\n"); 788 return count; 789 } 790 791 setDrainState(DrainState::Drained); 792 return 0; 793} 794 | |
795BaseCache * 796BaseCacheParams::create() 797{ 798 assert(tags); 799 800 return new Cache(this); 801} | 778BaseCache * 779BaseCacheParams::create() 780{ 781 assert(tags); 782 783 return new Cache(this); 784} |