1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43/** 44 * @file 45 * Definition of BaseCache functions. 46 */ 47 48#include "cpu/base.hh" 49#include "cpu/smt.hh" 50#include "debug/Cache.hh" |
51#include "debug/Drain.hh" |
52#include "mem/cache/base.hh" 53#include "mem/cache/mshr.hh" 54#include "sim/full_system.hh" 55 56using namespace std; 57 58BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 59 BaseCache *_cache, --- 688 unchanged lines hidden (view full) --- 748{ 749 int count = memSidePort->drain(de) + cpuSidePort->drain(de); 750 751 // Set status 752 if (count != 0) { 753 drainEvent = de; 754 755 changeState(SimObject::Draining); |
756 DPRINTF(Drain, "Cache not drained\n"); |
757 return count; 758 } 759 760 changeState(SimObject::Drained); 761 return 0; 762} |