1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33 * Definition of BaseCache functions. 34 */ 35 36#include "cpu/base.hh" 37#include "cpu/smt.hh" 38#include "debug/Cache.hh" 39#include "mem/cache/base.hh" 40#include "mem/cache/mshr.hh" |
41#include "sim/full_system.hh" |
42 43using namespace std; 44 45BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 46 const std::string &_label) 47 : SimpleTimingPort(_name, _cache), cache(_cache), |
48 label(_label), otherPort(NULL), 49 blocked(false), mustSendRetry(false) |
50{ 51} 52 53 54BaseCache::BaseCache(const Params *p) 55 : MemObject(p), 56 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 57 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, --- 7 unchanged lines hidden (view full) --- 65 noTargetMSHR(NULL), 66 missCount(p->max_miss_count), 67 drainEvent(NULL), 68 addrRange(p->addr_range), 69 _numCpus(p->num_cpus) 70{ 71} 72 |
73void 74BaseCache::CachePort::recvStatusChange(Port::Status status) 75{ 76 if (status == Port::RangeChange) { 77 otherPort->sendStatusChange(Port::RangeChange); 78 } 79} |
80 |
81 |
82bool 83BaseCache::CachePort::checkFunctional(PacketPtr pkt) 84{ 85 pkt->pushLabel(label); 86 bool done = SimpleTimingPort::checkFunctional(pkt); 87 pkt->popLabel(); 88 return done; 89} --- 32 unchanged lines hidden (view full) --- 122 DPRINTF(Cache, "Cache Unblocking\n"); 123 blocked = false; 124 if (mustSendRetry) 125 { 126 DPRINTF(Cache, "Cache Sending Retry\n"); 127 mustSendRetry = false; 128 SendRetryEvent *ev = new SendRetryEvent(this, true); 129 // @TODO: need to find a better time (next bus cycle?) |
130 schedule(ev, curTick() + 1); |
131 } 132} 133 134 135void 136BaseCache::init() 137{ 138 if (!cpuSidePort || !memSidePort) 139 panic("Cache not hooked up on both sides\n"); |
140 cpuSidePort->sendStatusChange(Port::RangeChange); |
141} 142 143 144void 145BaseCache::regStats() 146{ 147 using namespace Stats; 148 149 // Hit statistics 150 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 151 MemCmd cmd(access_idx); 152 const string &cstr = cmd.toString(); 153 154 hits[access_idx] |
155 .init(FullSystem ? (_numCpus + 1) : _numCpus) |
156 .name(name() + "." + cstr + "_hits") 157 .desc("number of " + cstr + " hits") 158 .flags(total | nozero | nonan) 159 ; 160 } 161 162// These macros make it easier to sum the right subset of commands and 163// to change the subset of commands that are considered "demand" vs --- 20 unchanged lines hidden (view full) --- 184 overallHits = demandHits + SUM_NON_DEMAND(hits); 185 186 // Miss statistics 187 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 188 MemCmd cmd(access_idx); 189 const string &cstr = cmd.toString(); 190 191 misses[access_idx] |
192 .init(FullSystem ? (_numCpus + 1) : _numCpus) |
193 .name(name() + "." + cstr + "_misses") 194 .desc("number of " + cstr + " misses") 195 .flags(total | nozero | nonan) 196 ; 197 } 198 199 demandMisses 200 .name(name() + ".demand_misses") --- 443 unchanged lines hidden --- |