| 1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 464 unchanged lines hidden (view full) --- 473 if (is_fill && !is_error) { 474 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 475 pkt->getAddr()); 476 477 const bool allocate = (writeAllocator && mshr->wasWholeLineWrite) ? 478 writeAllocator->allocate() : mshr->allocOnFill(); 479 blk = handleFill(pkt, blk, writebacks, allocate); 480 assert(blk != nullptr); |
| 481 ppFill->notify(pkt); |
| 482 } 483 484 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 485 // The block was marked not readable while there was a pending 486 // cache maintenance operation, restore its flag. 487 blk->status |= BlkReadable; 488 489 // This was a cache clean operation (without invalidate) --- 1729 unchanged lines hidden (view full) --- 2219 ; 2220} 2221 2222void 2223BaseCache::regProbePoints() 2224{ 2225 ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit"); 2226 ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss"); |
| 2227 ppFill = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Fill"); |
| 2228} 2229 2230/////////////// 2231// 2232// CpuSidePort 2233// 2234/////////////// 2235bool --- 213 unchanged lines hidden --- |