1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 99 unchanged lines hidden (view full) --- 108 // queue on every single allocation, whereas the write queue has 109 // as many reserve entries as we have MSHRs, since every MSHR may 110 // eventually require a writeback, and we do not check the write 111 // buffer before committing to an MSHR 112 113 // forward snoops is overridden in init() once we can query 114 // whether the connected master is actually snooping or not 115 |
116 tempBlock = new TempCacheBlk(blkSize); |
117 118 tags->setCache(this); 119 if (prefetcher) 120 prefetcher->setCache(this); 121} 122 123BaseCache::~BaseCache() 124{ |
125 delete tempBlock; 126} 127 128void 129BaseCache::CacheSlavePort::setBlocked() 130{ 131 assert(!blocked); 132 DPRINTF(CachePort, "Port is blocking new requests\n"); --- 2221 unchanged lines hidden --- |