1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1312 unchanged lines hidden (view full) --- 1321 1322 return pkt; 1323} 1324 1325 1326void 1327BaseCache::memWriteback() 1328{ |
1329 tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); |
1330} 1331 1332void 1333BaseCache::memInvalidate() 1334{ |
1335 tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); |
1336} 1337 1338bool 1339BaseCache::isDirty() const 1340{ |
1341 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); |
1342} 1343 |
1344void |
1345BaseCache::writebackVisitor(CacheBlk &blk) 1346{ 1347 if (blk.isDirty()) { 1348 assert(blk.isValid()); 1349 1350 Request request(tags->regenerateBlkAddr(&blk), 1351 blkSize, 0, Request::funcMasterId); 1352 request.taskId(blk.task_id); 1353 if (blk.isSecure()) { 1354 request.setFlags(Request::SECURE); 1355 } 1356 1357 Packet packet(&request, MemCmd::WriteReq); 1358 packet.dataStatic(blk.data); 1359 1360 memSidePort.sendFunctional(&packet); 1361 1362 blk.status &= ~BlkDirty; 1363 } |
1364} 1365 |
1366void |
1367BaseCache::invalidateVisitor(CacheBlk &blk) 1368{ 1369 if (blk.isDirty()) 1370 warn_once("Invalidating dirty cache lines. " \ 1371 "Expect things to break.\n"); 1372 1373 if (blk.isValid()) { 1374 assert(!blk.isDirty()); 1375 invalidateBlock(&blk); 1376 } |
1377} 1378 1379Tick 1380BaseCache::nextQueueReadyTime() const 1381{ 1382 Tick nextReady = std::min(mshrQueue.nextReadyTime(), 1383 writeBuffer.nextReadyTime()); 1384 --- 916 unchanged lines hidden --- |