1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 66 unchanged lines hidden (view full) --- 75 forwardLatency(p->hit_latency), 76 fillLatency(p->response_latency), 77 responseLatency(p->response_latency), 78 numTarget(p->tgts_per_mshr), 79 forwardSnoops(true), 80 isReadOnly(p->is_read_only), 81 blocked(0), 82 order(0), |
83 noTargetMSHR(nullptr), |
84 missCount(p->max_miss_count), 85 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 86 system(p->system) 87{ 88 // the MSHR queue has no reserve entries as we check the MSHR 89 // queue on every single allocation, whereas the write queue has 90 // as many reserve entries as we have MSHRs, since every MSHR may 91 // eventually require a writeback, and we do not check the write --- 667 unchanged lines hidden --- |