1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 92 unchanged lines hidden (view full) --- 101 102void 103BaseCache::CacheSlavePort::clearBlocked() 104{ 105 assert(blocked); 106 DPRINTF(CachePort, "Cache port %s accepting new requests\n", name()); 107 blocked = false; 108 if (mustSendRetry) { |
109 // @TODO: need to find a better time (next bus cycle?) 110 owner.schedule(sendRetryEvent, curTick() + 1); 111 } 112} 113 |
114void 115BaseCache::CacheSlavePort::processSendRetry() 116{ 117 DPRINTF(CachePort, "Cache port %s sending retry\n", name()); |
118 |
119 // reset the flag and call retry 120 mustSendRetry = false; 121 sendRetry(); 122} 123 |
124void 125BaseCache::init() 126{ 127 if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 128 fatal("Cache ports on %s are not connected\n", name()); 129 cpuSidePort->sendRangeChange(); 130} 131 --- 668 unchanged lines hidden --- |