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< Tick request_time = clockEdge(lat) + pkt->headerDelay;
---
> Tick request_time = clockEdge(lat);
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< BaseCache::calculateAccessLatency(const CacheBlk* blk,
---
> BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
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< Cycles lat(lookup_lat);
---
> Cycles lat(0);
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< // First access tags, then data
---
> // As soon as the access arrives, for sequential accesses first access
> // tags, then the data entry. In the case of parallel accesses the
> // latency is dictated by the slowest of tag and data latencies.
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< lat += dataLatency;
< // Latency is dictated by the slowest of tag and data latencies
---
> lat = ticksToCycles(delay) + lookup_lat + dataLatency;
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< lat = std::max(lookup_lat, dataLatency);
---
> lat = ticksToCycles(delay) + std::max(lookup_lat, dataLatency);
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> const Tick tick = curTick() + delay;
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< if (when_ready > curTick() &&
< ticksToCycles(when_ready - curTick()) > lat) {
< lat += ticksToCycles(when_ready - curTick());
---
> if (when_ready > tick &&
> ticksToCycles(when_ready - tick) > lat) {
> lat += ticksToCycles(when_ready - tick);
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> } else {
> // In case of a miss, apply lookup latency on top of the metadata
> // delay, as the access can only start when it arrives.
> lat = ticksToCycles(delay) + lookup_lat;
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< // Calculate access latency
< lat = calculateAccessLatency(blk, tag_latency);
---
> // Calculate access latency on top of when the packet arrives. This
> // takes into account the bus delay.
> lat = calculateAccessLatency(blk, pkt->headerDelay,
> tag_latency);