1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 */ 30 31/** 32 * @file 33 * Definition of BaseCache functions. 34 */ 35 36#include "cpu/base.hh" 37#include "cpu/smt.hh" 38#include "debug/Cache.hh" 39#include "mem/cache/base.hh" 40#include "mem/cache/mshr.hh" 41 42using namespace std; 43 44BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 45 const std::string &_label) 46 : SimpleTimingPort(_name, _cache), cache(_cache), 47 label(_label), otherPort(NULL), 48 blocked(false), mustSendRetry(false) 49{ 50} 51 52 53BaseCache::BaseCache(const Params *p) 54 : MemObject(p), 55 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 56 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 57 MSHRQueue_WriteBuffer), 58 blkSize(p->block_size), 59 hitLatency(p->latency), 60 numTarget(p->tgts_per_mshr), 61 forwardSnoops(p->forward_snoops), 62 isTopLevel(p->is_top_level), 63 blocked(0), 64 noTargetMSHR(NULL), 65 missCount(p->max_miss_count), 66 drainEvent(NULL), 67 addrRange(p->addr_range), 68 _numCpus(p->num_cpus) 69{ 70} 71 72void 73BaseCache::CachePort::recvStatusChange(Port::Status status) 74{ 75 if (status == Port::RangeChange) { 76 otherPort->sendStatusChange(Port::RangeChange); 77 } 78} 79 80 81bool 82BaseCache::CachePort::checkFunctional(PacketPtr pkt) 83{ 84 pkt->pushLabel(label); 85 bool done = SimpleTimingPort::checkFunctional(pkt); 86 pkt->popLabel(); 87 return done; 88} 89 90 91unsigned 92BaseCache::CachePort::deviceBlockSize() const 93{ 94 return cache->getBlockSize(); 95} 96 97 98bool 99BaseCache::CachePort::recvRetryCommon() 100{ 101 assert(waitingOnRetry); 102 waitingOnRetry = false; 103 return false; 104} 105 106 107void 108BaseCache::CachePort::setBlocked() 109{ 110 assert(!blocked); 111 DPRINTF(Cache, "Cache Blocking\n"); 112 blocked = true; 113 //Clear the retry flag 114 mustSendRetry = false; 115} 116 117void 118BaseCache::CachePort::clearBlocked() 119{ 120 assert(blocked); 121 DPRINTF(Cache, "Cache Unblocking\n"); 122 blocked = false; 123 if (mustSendRetry) 124 { 125 DPRINTF(Cache, "Cache Sending Retry\n"); 126 mustSendRetry = false; 127 SendRetryEvent *ev = new SendRetryEvent(this, true); 128 // @TODO: need to find a better time (next bus cycle?)
| 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 */ 30 31/** 32 * @file 33 * Definition of BaseCache functions. 34 */ 35 36#include "cpu/base.hh" 37#include "cpu/smt.hh" 38#include "debug/Cache.hh" 39#include "mem/cache/base.hh" 40#include "mem/cache/mshr.hh" 41 42using namespace std; 43 44BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 45 const std::string &_label) 46 : SimpleTimingPort(_name, _cache), cache(_cache), 47 label(_label), otherPort(NULL), 48 blocked(false), mustSendRetry(false) 49{ 50} 51 52 53BaseCache::BaseCache(const Params *p) 54 : MemObject(p), 55 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 56 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 57 MSHRQueue_WriteBuffer), 58 blkSize(p->block_size), 59 hitLatency(p->latency), 60 numTarget(p->tgts_per_mshr), 61 forwardSnoops(p->forward_snoops), 62 isTopLevel(p->is_top_level), 63 blocked(0), 64 noTargetMSHR(NULL), 65 missCount(p->max_miss_count), 66 drainEvent(NULL), 67 addrRange(p->addr_range), 68 _numCpus(p->num_cpus) 69{ 70} 71 72void 73BaseCache::CachePort::recvStatusChange(Port::Status status) 74{ 75 if (status == Port::RangeChange) { 76 otherPort->sendStatusChange(Port::RangeChange); 77 } 78} 79 80 81bool 82BaseCache::CachePort::checkFunctional(PacketPtr pkt) 83{ 84 pkt->pushLabel(label); 85 bool done = SimpleTimingPort::checkFunctional(pkt); 86 pkt->popLabel(); 87 return done; 88} 89 90 91unsigned 92BaseCache::CachePort::deviceBlockSize() const 93{ 94 return cache->getBlockSize(); 95} 96 97 98bool 99BaseCache::CachePort::recvRetryCommon() 100{ 101 assert(waitingOnRetry); 102 waitingOnRetry = false; 103 return false; 104} 105 106 107void 108BaseCache::CachePort::setBlocked() 109{ 110 assert(!blocked); 111 DPRINTF(Cache, "Cache Blocking\n"); 112 blocked = true; 113 //Clear the retry flag 114 mustSendRetry = false; 115} 116 117void 118BaseCache::CachePort::clearBlocked() 119{ 120 assert(blocked); 121 DPRINTF(Cache, "Cache Unblocking\n"); 122 blocked = false; 123 if (mustSendRetry) 124 { 125 DPRINTF(Cache, "Cache Sending Retry\n"); 126 mustSendRetry = false; 127 SendRetryEvent *ev = new SendRetryEvent(this, true); 128 // @TODO: need to find a better time (next bus cycle?)
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