1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Nikos Nikoleris 42 */ 43 44/** 45 * @file 46 * Definition of BaseCache functions. 47 */ 48 49#include "mem/cache/base.hh" 50 51#include "base/compiler.hh" 52#include "base/logging.hh" 53#include "debug/Cache.hh" 54#include "debug/CachePort.hh" 55#include "debug/CacheVerbose.hh" 56#include "mem/cache/mshr.hh" 57#include "mem/cache/prefetch/base.hh" 58#include "mem/cache/queue_entry.hh" 59#include "params/BaseCache.hh" 60#include "sim/core.hh" 61 62class BaseMasterPort; 63class BaseSlavePort; 64 65using namespace std; 66 67BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 68 BaseCache *_cache, 69 const std::string &_label) 70 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 71 blocked(false), mustSendRetry(false), 72 sendRetryEvent([this]{ processSendRetry(); }, _name) 73{ 74} 75 76BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 77 : MemObject(p), 78 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), 79 memSidePort(p->name + ".mem_side", this, "MemSidePort"), 80 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 81 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 82 tags(p->tags), 83 prefetcher(p->prefetcher), 84 prefetchOnAccess(p->prefetch_on_access), 85 writebackClean(p->writeback_clean), 86 tempBlockWriteback(nullptr), 87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 88 name(), false, 89 EventBase::Delayed_Writeback_Pri), 90 blkSize(blk_size), 91 lookupLatency(p->tag_latency), 92 dataLatency(p->data_latency), 93 forwardLatency(p->tag_latency), 94 fillLatency(p->data_latency), 95 responseLatency(p->response_latency), 96 numTarget(p->tgts_per_mshr), 97 forwardSnoops(true), 98 clusivity(p->clusivity), 99 isReadOnly(p->is_read_only), 100 blocked(0), 101 order(0), 102 noTargetMSHR(nullptr), 103 missCount(p->max_miss_count), 104 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 105 system(p->system) 106{ 107 // the MSHR queue has no reserve entries as we check the MSHR 108 // queue on every single allocation, whereas the write queue has 109 // as many reserve entries as we have MSHRs, since every MSHR may 110 // eventually require a writeback, and we do not check the write 111 // buffer before committing to an MSHR 112 113 // forward snoops is overridden in init() once we can query 114 // whether the connected master is actually snooping or not 115 116 tempBlock = new TempCacheBlk(); 117 tempBlock->data = new uint8_t[blkSize]; 118 119 tags->setCache(this); 120 if (prefetcher) 121 prefetcher->setCache(this); 122} 123 124BaseCache::~BaseCache() 125{ 126 delete [] tempBlock->data; 127 delete tempBlock; 128} 129 130void 131BaseCache::CacheSlavePort::setBlocked() 132{ 133 assert(!blocked); 134 DPRINTF(CachePort, "Port is blocking new requests\n"); 135 blocked = true; 136 // if we already scheduled a retry in this cycle, but it has not yet 137 // happened, cancel it 138 if (sendRetryEvent.scheduled()) { 139 owner.deschedule(sendRetryEvent); 140 DPRINTF(CachePort, "Port descheduled retry\n"); 141 mustSendRetry = true; 142 } 143} 144 145void 146BaseCache::CacheSlavePort::clearBlocked() 147{ 148 assert(blocked); 149 DPRINTF(CachePort, "Port is accepting new requests\n"); 150 blocked = false; 151 if (mustSendRetry) { 152 // @TODO: need to find a better time (next cycle?) 153 owner.schedule(sendRetryEvent, curTick() + 1); 154 } 155} 156 157void 158BaseCache::CacheSlavePort::processSendRetry() 159{ 160 DPRINTF(CachePort, "Port is sending retry\n"); 161 162 // reset the flag and call retry 163 mustSendRetry = false; 164 sendRetryReq(); 165} 166 167Addr 168BaseCache::regenerateBlkAddr(CacheBlk* blk) 169{ 170 if (blk != tempBlock) { 171 return tags->regenerateBlkAddr(blk); 172 } else { 173 return tempBlock->getAddr(); 174 } 175} 176 177void 178BaseCache::init() 179{ 180 if (!cpuSidePort.isConnected() || !memSidePort.isConnected()) 181 fatal("Cache ports on %s are not connected\n", name()); 182 cpuSidePort.sendRangeChange(); 183 forwardSnoops = cpuSidePort.isSnooping(); 184} 185 186BaseMasterPort & 187BaseCache::getMasterPort(const std::string &if_name, PortID idx) 188{ 189 if (if_name == "mem_side") { 190 return memSidePort; 191 } else { 192 return MemObject::getMasterPort(if_name, idx); 193 } 194} 195 196BaseSlavePort & 197BaseCache::getSlavePort(const std::string &if_name, PortID idx) 198{ 199 if (if_name == "cpu_side") { 200 return cpuSidePort; 201 } else { 202 return MemObject::getSlavePort(if_name, idx); 203 } 204} 205 206bool 207BaseCache::inRange(Addr addr) const 208{ 209 for (const auto& r : addrRanges) { 210 if (r.contains(addr)) { 211 return true; 212 } 213 } 214 return false; 215} 216 217void 218BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 219{ 220 if (pkt->needsResponse()) { 221 pkt->makeTimingResponse(); 222 // @todo: Make someone pay for this 223 pkt->headerDelay = pkt->payloadDelay = 0; 224 225 // In this case we are considering request_time that takes 226 // into account the delay of the xbar, if any, and just 227 // lat, neglecting responseLatency, modelling hit latency 228 // just as lookupLatency or or the value of lat overriden 229 // by access(), that calls accessBlock() function. 230 cpuSidePort.schedTimingResp(pkt, request_time, true); 231 } else { 232 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 233 pkt->print()); 234 235 // queue the packet for deletion, as the sending cache is 236 // still relying on it; if the block is found in access(), 237 // CleanEvict and Writeback messages will be deleted 238 // here as well 239 pendingDelete.reset(pkt); 240 } 241} 242 243void 244BaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 245 Tick forward_time, Tick request_time) 246{ 247 if (mshr) { 248 /// MSHR hit 249 /// @note writebacks will be checked in getNextMSHR() 250 /// for any conflicting requests to the same block 251 252 //@todo remove hw_pf here 253 254 // Coalesce unless it was a software prefetch (see above). 255 if (pkt) { 256 assert(!pkt->isWriteback()); 257 // CleanEvicts corresponding to blocks which have 258 // outstanding requests in MSHRs are simply sunk here 259 if (pkt->cmd == MemCmd::CleanEvict) { 260 pendingDelete.reset(pkt); 261 } else if (pkt->cmd == MemCmd::WriteClean) { 262 // A WriteClean should never coalesce with any 263 // outstanding cache maintenance requests. 264 265 // We use forward_time here because there is an 266 // uncached memory write, forwarded to WriteBuffer. 267 allocateWriteBuffer(pkt, forward_time); 268 } else { 269 DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 270 pkt->print()); 271 272 assert(pkt->req->masterId() < system->maxMasters()); 273 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 274 275 // We use forward_time here because it is the same 276 // considering new targets. We have multiple 277 // requests for the same address here. It 278 // specifies the latency to allocate an internal 279 // buffer and to schedule an event to the queued 280 // port and also takes into account the additional 281 // delay of the xbar. 282 mshr->allocateTarget(pkt, forward_time, order++, 283 allocOnFill(pkt->cmd)); 284 if (mshr->getNumTargets() == numTarget) { 285 noTargetMSHR = mshr; 286 setBlocked(Blocked_NoTargets); 287 // need to be careful with this... if this mshr isn't 288 // ready yet (i.e. time > curTick()), we don't want to 289 // move it ahead of mshrs that are ready 290 // mshrQueue.moveToFront(mshr); 291 } 292 } 293 } 294 } else { 295 // no MSHR 296 assert(pkt->req->masterId() < system->maxMasters()); 297 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 298 299 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) { 300 // We use forward_time here because there is an 301 // writeback or writeclean, forwarded to WriteBuffer. 302 allocateWriteBuffer(pkt, forward_time); 303 } else { 304 if (blk && blk->isValid()) { 305 // If we have a write miss to a valid block, we 306 // need to mark the block non-readable. Otherwise 307 // if we allow reads while there's an outstanding 308 // write miss, the read could return stale data 309 // out of the cache block... a more aggressive 310 // system could detect the overlap (if any) and 311 // forward data out of the MSHRs, but we don't do 312 // that yet. Note that we do need to leave the 313 // block valid so that it stays in the cache, in 314 // case we get an upgrade response (and hence no 315 // new data) when the write miss completes. 316 // As long as CPUs do proper store/load forwarding 317 // internally, and have a sufficiently weak memory 318 // model, this is probably unnecessary, but at some 319 // point it must have seemed like we needed it... 320 assert((pkt->needsWritable() && !blk->isWritable()) || 321 pkt->req->isCacheMaintenance()); 322 blk->status &= ~BlkReadable; 323 } 324 // Here we are using forward_time, modelling the latency of 325 // a miss (outbound) just as forwardLatency, neglecting the 326 // lookupLatency component. 327 allocateMissBuffer(pkt, forward_time); 328 } 329 } 330} 331 332void 333BaseCache::recvTimingReq(PacketPtr pkt) 334{ 335 // anything that is merely forwarded pays for the forward latency and 336 // the delay provided by the crossbar 337 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 338 339 // We use lookupLatency here because it is used to specify the latency 340 // to access. 341 Cycles lat = lookupLatency; 342 CacheBlk *blk = nullptr; 343 bool satisfied = false; 344 { 345 PacketList writebacks; 346 // Note that lat is passed by reference here. The function 347 // access() calls accessBlock() which can modify lat value. 348 satisfied = access(pkt, blk, lat, writebacks); 349 350 // copy writebacks to write buffer here to ensure they logically 351 // proceed anything happening below 352 doWritebacks(writebacks, forward_time); 353 } 354 355 // Here we charge the headerDelay that takes into account the latencies 356 // of the bus, if the packet comes from it. 357 // The latency charged it is just lat that is the value of lookupLatency 358 // modified by access() function, or if not just lookupLatency. 359 // In case of a hit we are neglecting response latency. 360 // In case of a miss we are neglecting forward latency. 361 Tick request_time = clockEdge(lat) + pkt->headerDelay; 362 // Here we reset the timing of the packet. 363 pkt->headerDelay = pkt->payloadDelay = 0; 364 // track time of availability of next prefetch, if any 365 Tick next_pf_time = MaxTick; 366 367 if (satisfied) { 368 // if need to notify the prefetcher we have to do it before 369 // anything else as later handleTimingReqHit might turn the 370 // packet in a response 371 if (prefetcher && 372 (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 373 if (blk) 374 blk->status &= ~BlkHWPrefetched; 375 376 // Don't notify on SWPrefetch 377 if (!pkt->cmd.isSWPrefetch()) { 378 assert(!pkt->req->isCacheMaintenance()); 379 next_pf_time = prefetcher->notify(pkt); 380 } 381 } 382 383 handleTimingReqHit(pkt, blk, request_time); 384 } else { 385 handleTimingReqMiss(pkt, blk, forward_time, request_time); 386 387 // We should call the prefetcher reguardless if the request is 388 // satisfied or not, reguardless if the request is in the MSHR 389 // or not. The request could be a ReadReq hit, but still not 390 // satisfied (potentially because of a prior write to the same 391 // cache line. So, even when not satisfied, there is an MSHR 392 // already allocated for this, we need to let the prefetcher 393 // know about the request 394 395 // Don't notify prefetcher on SWPrefetch or cache maintenance 396 // operations 397 if (prefetcher && pkt && 398 !pkt->cmd.isSWPrefetch() && 399 !pkt->req->isCacheMaintenance()) { 400 next_pf_time = prefetcher->notify(pkt); 401 } 402 } 403 404 if (next_pf_time != MaxTick) { 405 schedMemSideSendEvent(next_pf_time); 406 } 407} 408 409void 410BaseCache::handleUncacheableWriteResp(PacketPtr pkt) 411{ 412 Tick completion_time = clockEdge(responseLatency) + 413 pkt->headerDelay + pkt->payloadDelay; 414 415 // Reset the bus additional time as it is now accounted for 416 pkt->headerDelay = pkt->payloadDelay = 0; 417 418 cpuSidePort.schedTimingResp(pkt, completion_time, true); 419} 420 421void 422BaseCache::recvTimingResp(PacketPtr pkt) 423{ 424 assert(pkt->isResponse()); 425 426 // all header delay should be paid for by the crossbar, unless 427 // this is a prefetch response from above 428 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 429 "%s saw a non-zero packet delay\n", name()); 430 431 const bool is_error = pkt->isError(); 432 433 if (is_error) { 434 DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 435 pkt->print()); 436 } 437 438 DPRINTF(Cache, "%s: Handling response %s\n", __func__, 439 pkt->print()); 440 441 // if this is a write, we should be looking at an uncacheable 442 // write 443 if (pkt->isWrite()) { 444 assert(pkt->req->isUncacheable()); 445 handleUncacheableWriteResp(pkt); 446 return; 447 } 448 449 // we have dealt with any (uncacheable) writes above, from here on 450 // we know we are dealing with an MSHR due to a miss or a prefetch 451 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 452 assert(mshr); 453 454 if (mshr == noTargetMSHR) { 455 // we always clear at least one target 456 clearBlocked(Blocked_NoTargets); 457 noTargetMSHR = nullptr; 458 } 459 460 // Initial target is used just for stats 461 MSHR::Target *initial_tgt = mshr->getTarget(); 462 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 463 Tick miss_latency = curTick() - initial_tgt->recvTime; 464 465 if (pkt->req->isUncacheable()) { 466 assert(pkt->req->masterId() < system->maxMasters()); 467 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 468 miss_latency; 469 } else { 470 assert(pkt->req->masterId() < system->maxMasters()); 471 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 472 miss_latency; 473 } 474 475 PacketList writebacks; 476 477 bool is_fill = !mshr->isForward && 478 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 479 480 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 481 482 if (is_fill && !is_error) { 483 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 484 pkt->getAddr()); 485 486 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 487 assert(blk != nullptr); 488 } 489 490 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 491 // The block was marked not readable while there was a pending 492 // cache maintenance operation, restore its flag. 493 blk->status |= BlkReadable; 494 } 495 496 if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 497 // If at this point the referenced block is writable and the 498 // response is not a cache invalidate, we promote targets that 499 // were deferred as we couldn't guarrantee a writable copy 500 mshr->promoteWritable(); 501 } 502 503 serviceMSHRTargets(mshr, pkt, blk, writebacks); 504 505 if (mshr->promoteDeferredTargets()) { 506 // avoid later read getting stale data while write miss is 507 // outstanding.. see comment in timingAccess() 508 if (blk) { 509 blk->status &= ~BlkReadable; 510 } 511 mshrQueue.markPending(mshr); 512 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 513 } else { 514 // while we deallocate an mshr from the queue we still have to 515 // check the isFull condition before and after as we might 516 // have been using the reserved entries already 517 const bool was_full = mshrQueue.isFull(); 518 mshrQueue.deallocate(mshr); 519 if (was_full && !mshrQueue.isFull()) { 520 clearBlocked(Blocked_NoMSHRs); 521 } 522 523 // Request the bus for a prefetch if this deallocation freed enough 524 // MSHRs for a prefetch to take place 525 if (prefetcher && mshrQueue.canPrefetch()) { 526 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 527 clockEdge()); 528 if (next_pf_time != MaxTick) 529 schedMemSideSendEvent(next_pf_time); 530 } 531 } 532 533 // if we used temp block, check to see if its valid and then clear it out 534 if (blk == tempBlock && tempBlock->isValid()) { 535 evictBlock(blk, writebacks); 536 } 537 538 const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 539 // copy writebacks to write buffer 540 doWritebacks(writebacks, forward_time); 541 542 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 543 delete pkt; 544} 545 546 547Tick 548BaseCache::recvAtomic(PacketPtr pkt) 549{ 550 // We are in atomic mode so we pay just for lookupLatency here. 551 Cycles lat = lookupLatency; 552 553 // follow the same flow as in recvTimingReq, and check if a cache 554 // above us is responding 555 if (pkt->cacheResponding() && !pkt->isClean()) { 556 assert(!pkt->req->isCacheInvalidate()); 557 DPRINTF(Cache, "Cache above responding to %s: not responding\n", 558 pkt->print()); 559 560 // if a cache is responding, and it had the line in Owned 561 // rather than Modified state, we need to invalidate any 562 // copies that are not on the same path to memory 563 assert(pkt->needsWritable() && !pkt->responderHadWritable()); 564 lat += ticksToCycles(memSidePort.sendAtomic(pkt)); 565 566 return lat * clockPeriod(); 567 } 568 569 // should assert here that there are no outstanding MSHRs or 570 // writebacks... that would mean that someone used an atomic 571 // access in timing mode 572 573 CacheBlk *blk = nullptr; 574 PacketList writebacks; 575 bool satisfied = access(pkt, blk, lat, writebacks); 576 577 if (pkt->isClean() && blk && blk->isDirty()) { 578 // A cache clean opearation is looking for a dirty 579 // block. If a dirty block is encountered a WriteClean 580 // will update any copies to the path to the memory 581 // until the point of reference. 582 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 583 __func__, pkt->print(), blk->print()); 584 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 585 writebacks.push_back(wb_pkt); 586 pkt->setSatisfied(); 587 } 588 589 // handle writebacks resulting from the access here to ensure they 590 // logically proceed anything happening below 591 doWritebacksAtomic(writebacks); 592 assert(writebacks.empty()); 593 594 if (!satisfied) { 595 lat += handleAtomicReqMiss(pkt, blk, writebacks); 596 } 597 598 // Note that we don't invoke the prefetcher at all in atomic mode. 599 // It's not clear how to do it properly, particularly for 600 // prefetchers that aggressively generate prefetch candidates and 601 // rely on bandwidth contention to throttle them; these will tend 602 // to pollute the cache in atomic mode since there is no bandwidth 603 // contention. If we ever do want to enable prefetching in atomic 604 // mode, though, this is the place to do it... see timingAccess() 605 // for an example (though we'd want to issue the prefetch(es) 606 // immediately rather than calling requestMemSideBus() as we do 607 // there). 608 609 // do any writebacks resulting from the response handling 610 doWritebacksAtomic(writebacks); 611 612 // if we used temp block, check to see if its valid and if so 613 // clear it out, but only do so after the call to recvAtomic is 614 // finished so that any downstream observers (such as a snoop 615 // filter), first see the fill, and only then see the eviction 616 if (blk == tempBlock && tempBlock->isValid()) { 617 // the atomic CPU calls recvAtomic for fetch and load/store 618 // sequentuially, and we may already have a tempBlock 619 // writeback from the fetch that we have not yet sent 620 if (tempBlockWriteback) { 621 // if that is the case, write the prevoius one back, and 622 // do not schedule any new event 623 writebackTempBlockAtomic(); 624 } else { 625 // the writeback/clean eviction happens after the call to 626 // recvAtomic has finished (but before any successive 627 // calls), so that the response handling from the fill is 628 // allowed to happen first 629 schedule(writebackTempBlockAtomicEvent, curTick()); 630 } 631 632 tempBlockWriteback = evictBlock(blk); 633 } 634 635 if (pkt->needsResponse()) { 636 pkt->makeAtomicResponse(); 637 } 638 639 return lat * clockPeriod(); 640} 641 642void 643BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side) 644{ 645 Addr blk_addr = pkt->getBlockAddr(blkSize); 646 bool is_secure = pkt->isSecure(); 647 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 648 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 649 650 pkt->pushLabel(name()); 651 652 CacheBlkPrintWrapper cbpw(blk); 653 654 // Note that just because an L2/L3 has valid data doesn't mean an 655 // L1 doesn't have a more up-to-date modified copy that still 656 // needs to be found. As a result we always update the request if 657 // we have it, but only declare it satisfied if we are the owner. 658 659 // see if we have data at all (owned or otherwise) 660 bool have_data = blk && blk->isValid() 661 && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 662 blk->data); 663 664 // data we have is dirty if marked as such or if we have an 665 // in-service MSHR that is pending a modified line 666 bool have_dirty = 667 have_data && (blk->isDirty() || 668 (mshr && mshr->inService && mshr->isPendingModified())); 669 670 bool done = have_dirty || 671 cpuSidePort.checkFunctional(pkt) || 672 mshrQueue.checkFunctional(pkt, blk_addr) || 673 writeBuffer.checkFunctional(pkt, blk_addr) || 674 memSidePort.checkFunctional(pkt); 675 676 DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 677 (blk && blk->isValid()) ? "valid " : "", 678 have_data ? "data " : "", done ? "done " : ""); 679 680 // We're leaving the cache, so pop cache->name() label 681 pkt->popLabel(); 682 683 if (done) { 684 pkt->makeResponse(); 685 } else { 686 // if it came as a request from the CPU side then make sure it 687 // continues towards the memory side 688 if (from_cpu_side) { 689 memSidePort.sendFunctional(pkt); 690 } else if (cpuSidePort.isSnooping()) { 691 // if it came from the memory side, it must be a snoop request 692 // and we should only forward it if we are forwarding snoops 693 cpuSidePort.sendFunctionalSnoop(pkt); 694 } 695 } 696} 697 698 699void 700BaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 701{ 702 assert(pkt->isRequest()); 703 704 uint64_t overwrite_val; 705 bool overwrite_mem; 706 uint64_t condition_val64; 707 uint32_t condition_val32; 708 709 int offset = pkt->getOffset(blkSize); 710 uint8_t *blk_data = blk->data + offset; 711 712 assert(sizeof(uint64_t) >= pkt->getSize()); 713 714 overwrite_mem = true; 715 // keep a copy of our possible write value, and copy what is at the 716 // memory address into the packet 717 pkt->writeData((uint8_t *)&overwrite_val); 718 pkt->setData(blk_data); 719 720 if (pkt->req->isCondSwap()) { 721 if (pkt->getSize() == sizeof(uint64_t)) { 722 condition_val64 = pkt->req->getExtraData(); 723 overwrite_mem = !std::memcmp(&condition_val64, blk_data, 724 sizeof(uint64_t)); 725 } else if (pkt->getSize() == sizeof(uint32_t)) { 726 condition_val32 = (uint32_t)pkt->req->getExtraData(); 727 overwrite_mem = !std::memcmp(&condition_val32, blk_data, 728 sizeof(uint32_t)); 729 } else 730 panic("Invalid size for conditional read/write\n"); 731 } 732 733 if (overwrite_mem) { 734 std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 735 blk->status |= BlkDirty; 736 } 737} 738 739QueueEntry* 740BaseCache::getNextQueueEntry() 741{ 742 // Check both MSHR queue and write buffer for potential requests, 743 // note that null does not mean there is no request, it could 744 // simply be that it is not ready 745 MSHR *miss_mshr = mshrQueue.getNext(); 746 WriteQueueEntry *wq_entry = writeBuffer.getNext(); 747 748 // If we got a write buffer request ready, first priority is a 749 // full write buffer, otherwise we favour the miss requests 750 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 751 // need to search MSHR queue for conflicting earlier miss. 752 MSHR *conflict_mshr = 753 mshrQueue.findPending(wq_entry->blkAddr, 754 wq_entry->isSecure); 755 756 if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 757 // Service misses in order until conflict is cleared. 758 return conflict_mshr; 759 760 // @todo Note that we ignore the ready time of the conflict here 761 } 762 763 // No conflicts; issue write 764 return wq_entry; 765 } else if (miss_mshr) { 766 // need to check for conflicting earlier writeback 767 WriteQueueEntry *conflict_mshr = 768 writeBuffer.findPending(miss_mshr->blkAddr, 769 miss_mshr->isSecure); 770 if (conflict_mshr) { 771 // not sure why we don't check order here... it was in the 772 // original code but commented out. 773 774 // The only way this happens is if we are 775 // doing a write and we didn't have permissions 776 // then subsequently saw a writeback (owned got evicted) 777 // We need to make sure to perform the writeback first 778 // To preserve the dirty data, then we can issue the write 779 780 // should we return wq_entry here instead? I.e. do we 781 // have to flush writes in order? I don't think so... not 782 // for Alpha anyway. Maybe for x86? 783 return conflict_mshr; 784 785 // @todo Note that we ignore the ready time of the conflict here 786 } 787 788 // No conflicts; issue read 789 return miss_mshr; 790 } 791 792 // fall through... no pending requests. Try a prefetch. 793 assert(!miss_mshr && !wq_entry); 794 if (prefetcher && mshrQueue.canPrefetch()) { 795 // If we have a miss queue slot, we can try a prefetch 796 PacketPtr pkt = prefetcher->getPacket(); 797 if (pkt) { 798 Addr pf_addr = pkt->getBlockAddr(blkSize); 799 if (!tags->findBlock(pf_addr, pkt->isSecure()) && 800 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 801 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 802 // Update statistic on number of prefetches issued 803 // (hwpf_mshr_misses) 804 assert(pkt->req->masterId() < system->maxMasters()); 805 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 806 807 // allocate an MSHR and return it, note 808 // that we send the packet straight away, so do not 809 // schedule the send 810 return allocateMissBuffer(pkt, curTick(), false); 811 } else { 812 // free the request and packet 813 delete pkt; 814 } 815 } 816 } 817 818 return nullptr; 819} 820 821void 822BaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) 823{ 824 assert(pkt->isRequest()); 825 826 assert(blk && blk->isValid()); 827 // Occasionally this is not true... if we are a lower-level cache 828 // satisfying a string of Read and ReadEx requests from 829 // upper-level caches, a Read will mark the block as shared but we 830 // can satisfy a following ReadEx anyway since we can rely on the 831 // Read requester(s) to have buffered the ReadEx snoop and to 832 // invalidate their blocks after receiving them. 833 // assert(!pkt->needsWritable() || blk->isWritable()); 834 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 835 836 // Check RMW operations first since both isRead() and 837 // isWrite() will be true for them 838 if (pkt->cmd == MemCmd::SwapReq) { 839 cmpAndSwap(blk, pkt); 840 } else if (pkt->isWrite()) { 841 // we have the block in a writable state and can go ahead, 842 // note that the line may be also be considered writable in 843 // downstream caches along the path to memory, but always 844 // Exclusive, and never Modified 845 assert(blk->isWritable()); 846 // Write or WriteLine at the first cache with block in writable state 847 if (blk->checkWrite(pkt)) { 848 pkt->writeDataToBlock(blk->data, blkSize); 849 } 850 // Always mark the line as dirty (and thus transition to the 851 // Modified state) even if we are a failed StoreCond so we 852 // supply data to any snoops that have appended themselves to 853 // this cache before knowing the store will fail. 854 blk->status |= BlkDirty; 855 DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 856 } else if (pkt->isRead()) { 857 if (pkt->isLLSC()) { 858 blk->trackLoadLocked(pkt); 859 } 860 861 // all read responses have a data payload 862 assert(pkt->hasRespData()); 863 pkt->setDataFromBlock(blk->data, blkSize); 864 } else if (pkt->isUpgrade()) { 865 // sanity check 866 assert(!pkt->hasSharers()); 867 868 if (blk->isDirty()) { 869 // we were in the Owned state, and a cache above us that 870 // has the line in Shared state needs to be made aware 871 // that the data it already has is in fact dirty 872 pkt->setCacheResponding(); 873 blk->status &= ~BlkDirty; 874 } 875 } else { 876 assert(pkt->isInvalidate()); 877 invalidateBlock(blk); 878 DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 879 pkt->print()); 880 } 881} 882 883///////////////////////////////////////////////////// 884// 885// Access path: requests coming in from the CPU side 886// 887///////////////////////////////////////////////////// 888 889bool 890BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 891 PacketList &writebacks) 892{ 893 // sanity check 894 assert(pkt->isRequest()); 895 896 chatty_assert(!(isReadOnly && pkt->isWrite()), 897 "Should never see a write in a read-only cache %s\n", 898 name()); 899 900 // Here lat is the value passed as parameter to accessBlock() function 901 // that can modify its value. 902 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 903 904 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 905 blk ? "hit " + blk->print() : "miss"); 906 907 if (pkt->req->isCacheMaintenance()) { 908 // A cache maintenance operation is always forwarded to the 909 // memory below even if the block is found in dirty state. 910 911 // We defer any changes to the state of the block until we 912 // create and mark as in service the mshr for the downstream 913 // packet. 914 return false; 915 } 916 917 if (pkt->isEviction()) { 918 // We check for presence of block in above caches before issuing 919 // Writeback or CleanEvict to write buffer. Therefore the only 920 // possible cases can be of a CleanEvict packet coming from above 921 // encountering a Writeback generated in this cache peer cache and 922 // waiting in the write buffer. Cases of upper level peer caches 923 // generating CleanEvict and Writeback or simply CleanEvict and 924 // CleanEvict almost simultaneously will be caught by snoops sent out 925 // by crossbar. 926 WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 927 pkt->isSecure()); 928 if (wb_entry) { 929 assert(wb_entry->getNumTargets() == 1); 930 PacketPtr wbPkt = wb_entry->getTarget()->pkt; 931 assert(wbPkt->isWriteback()); 932 933 if (pkt->isCleanEviction()) { 934 // The CleanEvict and WritebackClean snoops into other 935 // peer caches of the same level while traversing the 936 // crossbar. If a copy of the block is found, the 937 // packet is deleted in the crossbar. Hence, none of 938 // the other upper level caches connected to this 939 // cache have the block, so we can clear the 940 // BLOCK_CACHED flag in the Writeback if set and 941 // discard the CleanEvict by returning true. 942 wbPkt->clearBlockCached(); 943 return true; 944 } else { 945 assert(pkt->cmd == MemCmd::WritebackDirty); 946 // Dirty writeback from above trumps our clean 947 // writeback... discard here 948 // Note: markInService will remove entry from writeback buffer. 949 markInService(wb_entry); 950 delete wbPkt; 951 } 952 } 953 } 954 955 // Writeback handling is special case. We can write the block into 956 // the cache without having a writeable copy (or any copy at all). 957 if (pkt->isWriteback()) { 958 assert(blkSize == pkt->getSize()); 959 960 // we could get a clean writeback while we are having 961 // outstanding accesses to a block, do the simple thing for 962 // now and drop the clean writeback so that we do not upset 963 // any ordering/decisions about ownership already taken 964 if (pkt->cmd == MemCmd::WritebackClean && 965 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 966 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 967 "dropping\n", pkt->getAddr()); 968 return true; 969 } 970 971 if (!blk) { 972 // need to do a replacement
| 1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Nikos Nikoleris 42 */ 43 44/** 45 * @file 46 * Definition of BaseCache functions. 47 */ 48 49#include "mem/cache/base.hh" 50 51#include "base/compiler.hh" 52#include "base/logging.hh" 53#include "debug/Cache.hh" 54#include "debug/CachePort.hh" 55#include "debug/CacheVerbose.hh" 56#include "mem/cache/mshr.hh" 57#include "mem/cache/prefetch/base.hh" 58#include "mem/cache/queue_entry.hh" 59#include "params/BaseCache.hh" 60#include "sim/core.hh" 61 62class BaseMasterPort; 63class BaseSlavePort; 64 65using namespace std; 66 67BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 68 BaseCache *_cache, 69 const std::string &_label) 70 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 71 blocked(false), mustSendRetry(false), 72 sendRetryEvent([this]{ processSendRetry(); }, _name) 73{ 74} 75 76BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 77 : MemObject(p), 78 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), 79 memSidePort(p->name + ".mem_side", this, "MemSidePort"), 80 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 81 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 82 tags(p->tags), 83 prefetcher(p->prefetcher), 84 prefetchOnAccess(p->prefetch_on_access), 85 writebackClean(p->writeback_clean), 86 tempBlockWriteback(nullptr), 87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 88 name(), false, 89 EventBase::Delayed_Writeback_Pri), 90 blkSize(blk_size), 91 lookupLatency(p->tag_latency), 92 dataLatency(p->data_latency), 93 forwardLatency(p->tag_latency), 94 fillLatency(p->data_latency), 95 responseLatency(p->response_latency), 96 numTarget(p->tgts_per_mshr), 97 forwardSnoops(true), 98 clusivity(p->clusivity), 99 isReadOnly(p->is_read_only), 100 blocked(0), 101 order(0), 102 noTargetMSHR(nullptr), 103 missCount(p->max_miss_count), 104 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 105 system(p->system) 106{ 107 // the MSHR queue has no reserve entries as we check the MSHR 108 // queue on every single allocation, whereas the write queue has 109 // as many reserve entries as we have MSHRs, since every MSHR may 110 // eventually require a writeback, and we do not check the write 111 // buffer before committing to an MSHR 112 113 // forward snoops is overridden in init() once we can query 114 // whether the connected master is actually snooping or not 115 116 tempBlock = new TempCacheBlk(); 117 tempBlock->data = new uint8_t[blkSize]; 118 119 tags->setCache(this); 120 if (prefetcher) 121 prefetcher->setCache(this); 122} 123 124BaseCache::~BaseCache() 125{ 126 delete [] tempBlock->data; 127 delete tempBlock; 128} 129 130void 131BaseCache::CacheSlavePort::setBlocked() 132{ 133 assert(!blocked); 134 DPRINTF(CachePort, "Port is blocking new requests\n"); 135 blocked = true; 136 // if we already scheduled a retry in this cycle, but it has not yet 137 // happened, cancel it 138 if (sendRetryEvent.scheduled()) { 139 owner.deschedule(sendRetryEvent); 140 DPRINTF(CachePort, "Port descheduled retry\n"); 141 mustSendRetry = true; 142 } 143} 144 145void 146BaseCache::CacheSlavePort::clearBlocked() 147{ 148 assert(blocked); 149 DPRINTF(CachePort, "Port is accepting new requests\n"); 150 blocked = false; 151 if (mustSendRetry) { 152 // @TODO: need to find a better time (next cycle?) 153 owner.schedule(sendRetryEvent, curTick() + 1); 154 } 155} 156 157void 158BaseCache::CacheSlavePort::processSendRetry() 159{ 160 DPRINTF(CachePort, "Port is sending retry\n"); 161 162 // reset the flag and call retry 163 mustSendRetry = false; 164 sendRetryReq(); 165} 166 167Addr 168BaseCache::regenerateBlkAddr(CacheBlk* blk) 169{ 170 if (blk != tempBlock) { 171 return tags->regenerateBlkAddr(blk); 172 } else { 173 return tempBlock->getAddr(); 174 } 175} 176 177void 178BaseCache::init() 179{ 180 if (!cpuSidePort.isConnected() || !memSidePort.isConnected()) 181 fatal("Cache ports on %s are not connected\n", name()); 182 cpuSidePort.sendRangeChange(); 183 forwardSnoops = cpuSidePort.isSnooping(); 184} 185 186BaseMasterPort & 187BaseCache::getMasterPort(const std::string &if_name, PortID idx) 188{ 189 if (if_name == "mem_side") { 190 return memSidePort; 191 } else { 192 return MemObject::getMasterPort(if_name, idx); 193 } 194} 195 196BaseSlavePort & 197BaseCache::getSlavePort(const std::string &if_name, PortID idx) 198{ 199 if (if_name == "cpu_side") { 200 return cpuSidePort; 201 } else { 202 return MemObject::getSlavePort(if_name, idx); 203 } 204} 205 206bool 207BaseCache::inRange(Addr addr) const 208{ 209 for (const auto& r : addrRanges) { 210 if (r.contains(addr)) { 211 return true; 212 } 213 } 214 return false; 215} 216 217void 218BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 219{ 220 if (pkt->needsResponse()) { 221 pkt->makeTimingResponse(); 222 // @todo: Make someone pay for this 223 pkt->headerDelay = pkt->payloadDelay = 0; 224 225 // In this case we are considering request_time that takes 226 // into account the delay of the xbar, if any, and just 227 // lat, neglecting responseLatency, modelling hit latency 228 // just as lookupLatency or or the value of lat overriden 229 // by access(), that calls accessBlock() function. 230 cpuSidePort.schedTimingResp(pkt, request_time, true); 231 } else { 232 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 233 pkt->print()); 234 235 // queue the packet for deletion, as the sending cache is 236 // still relying on it; if the block is found in access(), 237 // CleanEvict and Writeback messages will be deleted 238 // here as well 239 pendingDelete.reset(pkt); 240 } 241} 242 243void 244BaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 245 Tick forward_time, Tick request_time) 246{ 247 if (mshr) { 248 /// MSHR hit 249 /// @note writebacks will be checked in getNextMSHR() 250 /// for any conflicting requests to the same block 251 252 //@todo remove hw_pf here 253 254 // Coalesce unless it was a software prefetch (see above). 255 if (pkt) { 256 assert(!pkt->isWriteback()); 257 // CleanEvicts corresponding to blocks which have 258 // outstanding requests in MSHRs are simply sunk here 259 if (pkt->cmd == MemCmd::CleanEvict) { 260 pendingDelete.reset(pkt); 261 } else if (pkt->cmd == MemCmd::WriteClean) { 262 // A WriteClean should never coalesce with any 263 // outstanding cache maintenance requests. 264 265 // We use forward_time here because there is an 266 // uncached memory write, forwarded to WriteBuffer. 267 allocateWriteBuffer(pkt, forward_time); 268 } else { 269 DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 270 pkt->print()); 271 272 assert(pkt->req->masterId() < system->maxMasters()); 273 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 274 275 // We use forward_time here because it is the same 276 // considering new targets. We have multiple 277 // requests for the same address here. It 278 // specifies the latency to allocate an internal 279 // buffer and to schedule an event to the queued 280 // port and also takes into account the additional 281 // delay of the xbar. 282 mshr->allocateTarget(pkt, forward_time, order++, 283 allocOnFill(pkt->cmd)); 284 if (mshr->getNumTargets() == numTarget) { 285 noTargetMSHR = mshr; 286 setBlocked(Blocked_NoTargets); 287 // need to be careful with this... if this mshr isn't 288 // ready yet (i.e. time > curTick()), we don't want to 289 // move it ahead of mshrs that are ready 290 // mshrQueue.moveToFront(mshr); 291 } 292 } 293 } 294 } else { 295 // no MSHR 296 assert(pkt->req->masterId() < system->maxMasters()); 297 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 298 299 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) { 300 // We use forward_time here because there is an 301 // writeback or writeclean, forwarded to WriteBuffer. 302 allocateWriteBuffer(pkt, forward_time); 303 } else { 304 if (blk && blk->isValid()) { 305 // If we have a write miss to a valid block, we 306 // need to mark the block non-readable. Otherwise 307 // if we allow reads while there's an outstanding 308 // write miss, the read could return stale data 309 // out of the cache block... a more aggressive 310 // system could detect the overlap (if any) and 311 // forward data out of the MSHRs, but we don't do 312 // that yet. Note that we do need to leave the 313 // block valid so that it stays in the cache, in 314 // case we get an upgrade response (and hence no 315 // new data) when the write miss completes. 316 // As long as CPUs do proper store/load forwarding 317 // internally, and have a sufficiently weak memory 318 // model, this is probably unnecessary, but at some 319 // point it must have seemed like we needed it... 320 assert((pkt->needsWritable() && !blk->isWritable()) || 321 pkt->req->isCacheMaintenance()); 322 blk->status &= ~BlkReadable; 323 } 324 // Here we are using forward_time, modelling the latency of 325 // a miss (outbound) just as forwardLatency, neglecting the 326 // lookupLatency component. 327 allocateMissBuffer(pkt, forward_time); 328 } 329 } 330} 331 332void 333BaseCache::recvTimingReq(PacketPtr pkt) 334{ 335 // anything that is merely forwarded pays for the forward latency and 336 // the delay provided by the crossbar 337 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 338 339 // We use lookupLatency here because it is used to specify the latency 340 // to access. 341 Cycles lat = lookupLatency; 342 CacheBlk *blk = nullptr; 343 bool satisfied = false; 344 { 345 PacketList writebacks; 346 // Note that lat is passed by reference here. The function 347 // access() calls accessBlock() which can modify lat value. 348 satisfied = access(pkt, blk, lat, writebacks); 349 350 // copy writebacks to write buffer here to ensure they logically 351 // proceed anything happening below 352 doWritebacks(writebacks, forward_time); 353 } 354 355 // Here we charge the headerDelay that takes into account the latencies 356 // of the bus, if the packet comes from it. 357 // The latency charged it is just lat that is the value of lookupLatency 358 // modified by access() function, or if not just lookupLatency. 359 // In case of a hit we are neglecting response latency. 360 // In case of a miss we are neglecting forward latency. 361 Tick request_time = clockEdge(lat) + pkt->headerDelay; 362 // Here we reset the timing of the packet. 363 pkt->headerDelay = pkt->payloadDelay = 0; 364 // track time of availability of next prefetch, if any 365 Tick next_pf_time = MaxTick; 366 367 if (satisfied) { 368 // if need to notify the prefetcher we have to do it before 369 // anything else as later handleTimingReqHit might turn the 370 // packet in a response 371 if (prefetcher && 372 (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 373 if (blk) 374 blk->status &= ~BlkHWPrefetched; 375 376 // Don't notify on SWPrefetch 377 if (!pkt->cmd.isSWPrefetch()) { 378 assert(!pkt->req->isCacheMaintenance()); 379 next_pf_time = prefetcher->notify(pkt); 380 } 381 } 382 383 handleTimingReqHit(pkt, blk, request_time); 384 } else { 385 handleTimingReqMiss(pkt, blk, forward_time, request_time); 386 387 // We should call the prefetcher reguardless if the request is 388 // satisfied or not, reguardless if the request is in the MSHR 389 // or not. The request could be a ReadReq hit, but still not 390 // satisfied (potentially because of a prior write to the same 391 // cache line. So, even when not satisfied, there is an MSHR 392 // already allocated for this, we need to let the prefetcher 393 // know about the request 394 395 // Don't notify prefetcher on SWPrefetch or cache maintenance 396 // operations 397 if (prefetcher && pkt && 398 !pkt->cmd.isSWPrefetch() && 399 !pkt->req->isCacheMaintenance()) { 400 next_pf_time = prefetcher->notify(pkt); 401 } 402 } 403 404 if (next_pf_time != MaxTick) { 405 schedMemSideSendEvent(next_pf_time); 406 } 407} 408 409void 410BaseCache::handleUncacheableWriteResp(PacketPtr pkt) 411{ 412 Tick completion_time = clockEdge(responseLatency) + 413 pkt->headerDelay + pkt->payloadDelay; 414 415 // Reset the bus additional time as it is now accounted for 416 pkt->headerDelay = pkt->payloadDelay = 0; 417 418 cpuSidePort.schedTimingResp(pkt, completion_time, true); 419} 420 421void 422BaseCache::recvTimingResp(PacketPtr pkt) 423{ 424 assert(pkt->isResponse()); 425 426 // all header delay should be paid for by the crossbar, unless 427 // this is a prefetch response from above 428 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 429 "%s saw a non-zero packet delay\n", name()); 430 431 const bool is_error = pkt->isError(); 432 433 if (is_error) { 434 DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 435 pkt->print()); 436 } 437 438 DPRINTF(Cache, "%s: Handling response %s\n", __func__, 439 pkt->print()); 440 441 // if this is a write, we should be looking at an uncacheable 442 // write 443 if (pkt->isWrite()) { 444 assert(pkt->req->isUncacheable()); 445 handleUncacheableWriteResp(pkt); 446 return; 447 } 448 449 // we have dealt with any (uncacheable) writes above, from here on 450 // we know we are dealing with an MSHR due to a miss or a prefetch 451 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 452 assert(mshr); 453 454 if (mshr == noTargetMSHR) { 455 // we always clear at least one target 456 clearBlocked(Blocked_NoTargets); 457 noTargetMSHR = nullptr; 458 } 459 460 // Initial target is used just for stats 461 MSHR::Target *initial_tgt = mshr->getTarget(); 462 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 463 Tick miss_latency = curTick() - initial_tgt->recvTime; 464 465 if (pkt->req->isUncacheable()) { 466 assert(pkt->req->masterId() < system->maxMasters()); 467 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 468 miss_latency; 469 } else { 470 assert(pkt->req->masterId() < system->maxMasters()); 471 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 472 miss_latency; 473 } 474 475 PacketList writebacks; 476 477 bool is_fill = !mshr->isForward && 478 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 479 480 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 481 482 if (is_fill && !is_error) { 483 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 484 pkt->getAddr()); 485 486 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 487 assert(blk != nullptr); 488 } 489 490 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 491 // The block was marked not readable while there was a pending 492 // cache maintenance operation, restore its flag. 493 blk->status |= BlkReadable; 494 } 495 496 if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 497 // If at this point the referenced block is writable and the 498 // response is not a cache invalidate, we promote targets that 499 // were deferred as we couldn't guarrantee a writable copy 500 mshr->promoteWritable(); 501 } 502 503 serviceMSHRTargets(mshr, pkt, blk, writebacks); 504 505 if (mshr->promoteDeferredTargets()) { 506 // avoid later read getting stale data while write miss is 507 // outstanding.. see comment in timingAccess() 508 if (blk) { 509 blk->status &= ~BlkReadable; 510 } 511 mshrQueue.markPending(mshr); 512 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 513 } else { 514 // while we deallocate an mshr from the queue we still have to 515 // check the isFull condition before and after as we might 516 // have been using the reserved entries already 517 const bool was_full = mshrQueue.isFull(); 518 mshrQueue.deallocate(mshr); 519 if (was_full && !mshrQueue.isFull()) { 520 clearBlocked(Blocked_NoMSHRs); 521 } 522 523 // Request the bus for a prefetch if this deallocation freed enough 524 // MSHRs for a prefetch to take place 525 if (prefetcher && mshrQueue.canPrefetch()) { 526 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 527 clockEdge()); 528 if (next_pf_time != MaxTick) 529 schedMemSideSendEvent(next_pf_time); 530 } 531 } 532 533 // if we used temp block, check to see if its valid and then clear it out 534 if (blk == tempBlock && tempBlock->isValid()) { 535 evictBlock(blk, writebacks); 536 } 537 538 const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 539 // copy writebacks to write buffer 540 doWritebacks(writebacks, forward_time); 541 542 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 543 delete pkt; 544} 545 546 547Tick 548BaseCache::recvAtomic(PacketPtr pkt) 549{ 550 // We are in atomic mode so we pay just for lookupLatency here. 551 Cycles lat = lookupLatency; 552 553 // follow the same flow as in recvTimingReq, and check if a cache 554 // above us is responding 555 if (pkt->cacheResponding() && !pkt->isClean()) { 556 assert(!pkt->req->isCacheInvalidate()); 557 DPRINTF(Cache, "Cache above responding to %s: not responding\n", 558 pkt->print()); 559 560 // if a cache is responding, and it had the line in Owned 561 // rather than Modified state, we need to invalidate any 562 // copies that are not on the same path to memory 563 assert(pkt->needsWritable() && !pkt->responderHadWritable()); 564 lat += ticksToCycles(memSidePort.sendAtomic(pkt)); 565 566 return lat * clockPeriod(); 567 } 568 569 // should assert here that there are no outstanding MSHRs or 570 // writebacks... that would mean that someone used an atomic 571 // access in timing mode 572 573 CacheBlk *blk = nullptr; 574 PacketList writebacks; 575 bool satisfied = access(pkt, blk, lat, writebacks); 576 577 if (pkt->isClean() && blk && blk->isDirty()) { 578 // A cache clean opearation is looking for a dirty 579 // block. If a dirty block is encountered a WriteClean 580 // will update any copies to the path to the memory 581 // until the point of reference. 582 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 583 __func__, pkt->print(), blk->print()); 584 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 585 writebacks.push_back(wb_pkt); 586 pkt->setSatisfied(); 587 } 588 589 // handle writebacks resulting from the access here to ensure they 590 // logically proceed anything happening below 591 doWritebacksAtomic(writebacks); 592 assert(writebacks.empty()); 593 594 if (!satisfied) { 595 lat += handleAtomicReqMiss(pkt, blk, writebacks); 596 } 597 598 // Note that we don't invoke the prefetcher at all in atomic mode. 599 // It's not clear how to do it properly, particularly for 600 // prefetchers that aggressively generate prefetch candidates and 601 // rely on bandwidth contention to throttle them; these will tend 602 // to pollute the cache in atomic mode since there is no bandwidth 603 // contention. If we ever do want to enable prefetching in atomic 604 // mode, though, this is the place to do it... see timingAccess() 605 // for an example (though we'd want to issue the prefetch(es) 606 // immediately rather than calling requestMemSideBus() as we do 607 // there). 608 609 // do any writebacks resulting from the response handling 610 doWritebacksAtomic(writebacks); 611 612 // if we used temp block, check to see if its valid and if so 613 // clear it out, but only do so after the call to recvAtomic is 614 // finished so that any downstream observers (such as a snoop 615 // filter), first see the fill, and only then see the eviction 616 if (blk == tempBlock && tempBlock->isValid()) { 617 // the atomic CPU calls recvAtomic for fetch and load/store 618 // sequentuially, and we may already have a tempBlock 619 // writeback from the fetch that we have not yet sent 620 if (tempBlockWriteback) { 621 // if that is the case, write the prevoius one back, and 622 // do not schedule any new event 623 writebackTempBlockAtomic(); 624 } else { 625 // the writeback/clean eviction happens after the call to 626 // recvAtomic has finished (but before any successive 627 // calls), so that the response handling from the fill is 628 // allowed to happen first 629 schedule(writebackTempBlockAtomicEvent, curTick()); 630 } 631 632 tempBlockWriteback = evictBlock(blk); 633 } 634 635 if (pkt->needsResponse()) { 636 pkt->makeAtomicResponse(); 637 } 638 639 return lat * clockPeriod(); 640} 641 642void 643BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side) 644{ 645 Addr blk_addr = pkt->getBlockAddr(blkSize); 646 bool is_secure = pkt->isSecure(); 647 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 648 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 649 650 pkt->pushLabel(name()); 651 652 CacheBlkPrintWrapper cbpw(blk); 653 654 // Note that just because an L2/L3 has valid data doesn't mean an 655 // L1 doesn't have a more up-to-date modified copy that still 656 // needs to be found. As a result we always update the request if 657 // we have it, but only declare it satisfied if we are the owner. 658 659 // see if we have data at all (owned or otherwise) 660 bool have_data = blk && blk->isValid() 661 && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 662 blk->data); 663 664 // data we have is dirty if marked as such or if we have an 665 // in-service MSHR that is pending a modified line 666 bool have_dirty = 667 have_data && (blk->isDirty() || 668 (mshr && mshr->inService && mshr->isPendingModified())); 669 670 bool done = have_dirty || 671 cpuSidePort.checkFunctional(pkt) || 672 mshrQueue.checkFunctional(pkt, blk_addr) || 673 writeBuffer.checkFunctional(pkt, blk_addr) || 674 memSidePort.checkFunctional(pkt); 675 676 DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 677 (blk && blk->isValid()) ? "valid " : "", 678 have_data ? "data " : "", done ? "done " : ""); 679 680 // We're leaving the cache, so pop cache->name() label 681 pkt->popLabel(); 682 683 if (done) { 684 pkt->makeResponse(); 685 } else { 686 // if it came as a request from the CPU side then make sure it 687 // continues towards the memory side 688 if (from_cpu_side) { 689 memSidePort.sendFunctional(pkt); 690 } else if (cpuSidePort.isSnooping()) { 691 // if it came from the memory side, it must be a snoop request 692 // and we should only forward it if we are forwarding snoops 693 cpuSidePort.sendFunctionalSnoop(pkt); 694 } 695 } 696} 697 698 699void 700BaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 701{ 702 assert(pkt->isRequest()); 703 704 uint64_t overwrite_val; 705 bool overwrite_mem; 706 uint64_t condition_val64; 707 uint32_t condition_val32; 708 709 int offset = pkt->getOffset(blkSize); 710 uint8_t *blk_data = blk->data + offset; 711 712 assert(sizeof(uint64_t) >= pkt->getSize()); 713 714 overwrite_mem = true; 715 // keep a copy of our possible write value, and copy what is at the 716 // memory address into the packet 717 pkt->writeData((uint8_t *)&overwrite_val); 718 pkt->setData(blk_data); 719 720 if (pkt->req->isCondSwap()) { 721 if (pkt->getSize() == sizeof(uint64_t)) { 722 condition_val64 = pkt->req->getExtraData(); 723 overwrite_mem = !std::memcmp(&condition_val64, blk_data, 724 sizeof(uint64_t)); 725 } else if (pkt->getSize() == sizeof(uint32_t)) { 726 condition_val32 = (uint32_t)pkt->req->getExtraData(); 727 overwrite_mem = !std::memcmp(&condition_val32, blk_data, 728 sizeof(uint32_t)); 729 } else 730 panic("Invalid size for conditional read/write\n"); 731 } 732 733 if (overwrite_mem) { 734 std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 735 blk->status |= BlkDirty; 736 } 737} 738 739QueueEntry* 740BaseCache::getNextQueueEntry() 741{ 742 // Check both MSHR queue and write buffer for potential requests, 743 // note that null does not mean there is no request, it could 744 // simply be that it is not ready 745 MSHR *miss_mshr = mshrQueue.getNext(); 746 WriteQueueEntry *wq_entry = writeBuffer.getNext(); 747 748 // If we got a write buffer request ready, first priority is a 749 // full write buffer, otherwise we favour the miss requests 750 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 751 // need to search MSHR queue for conflicting earlier miss. 752 MSHR *conflict_mshr = 753 mshrQueue.findPending(wq_entry->blkAddr, 754 wq_entry->isSecure); 755 756 if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 757 // Service misses in order until conflict is cleared. 758 return conflict_mshr; 759 760 // @todo Note that we ignore the ready time of the conflict here 761 } 762 763 // No conflicts; issue write 764 return wq_entry; 765 } else if (miss_mshr) { 766 // need to check for conflicting earlier writeback 767 WriteQueueEntry *conflict_mshr = 768 writeBuffer.findPending(miss_mshr->blkAddr, 769 miss_mshr->isSecure); 770 if (conflict_mshr) { 771 // not sure why we don't check order here... it was in the 772 // original code but commented out. 773 774 // The only way this happens is if we are 775 // doing a write and we didn't have permissions 776 // then subsequently saw a writeback (owned got evicted) 777 // We need to make sure to perform the writeback first 778 // To preserve the dirty data, then we can issue the write 779 780 // should we return wq_entry here instead? I.e. do we 781 // have to flush writes in order? I don't think so... not 782 // for Alpha anyway. Maybe for x86? 783 return conflict_mshr; 784 785 // @todo Note that we ignore the ready time of the conflict here 786 } 787 788 // No conflicts; issue read 789 return miss_mshr; 790 } 791 792 // fall through... no pending requests. Try a prefetch. 793 assert(!miss_mshr && !wq_entry); 794 if (prefetcher && mshrQueue.canPrefetch()) { 795 // If we have a miss queue slot, we can try a prefetch 796 PacketPtr pkt = prefetcher->getPacket(); 797 if (pkt) { 798 Addr pf_addr = pkt->getBlockAddr(blkSize); 799 if (!tags->findBlock(pf_addr, pkt->isSecure()) && 800 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 801 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 802 // Update statistic on number of prefetches issued 803 // (hwpf_mshr_misses) 804 assert(pkt->req->masterId() < system->maxMasters()); 805 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 806 807 // allocate an MSHR and return it, note 808 // that we send the packet straight away, so do not 809 // schedule the send 810 return allocateMissBuffer(pkt, curTick(), false); 811 } else { 812 // free the request and packet 813 delete pkt; 814 } 815 } 816 } 817 818 return nullptr; 819} 820 821void 822BaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) 823{ 824 assert(pkt->isRequest()); 825 826 assert(blk && blk->isValid()); 827 // Occasionally this is not true... if we are a lower-level cache 828 // satisfying a string of Read and ReadEx requests from 829 // upper-level caches, a Read will mark the block as shared but we 830 // can satisfy a following ReadEx anyway since we can rely on the 831 // Read requester(s) to have buffered the ReadEx snoop and to 832 // invalidate their blocks after receiving them. 833 // assert(!pkt->needsWritable() || blk->isWritable()); 834 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 835 836 // Check RMW operations first since both isRead() and 837 // isWrite() will be true for them 838 if (pkt->cmd == MemCmd::SwapReq) { 839 cmpAndSwap(blk, pkt); 840 } else if (pkt->isWrite()) { 841 // we have the block in a writable state and can go ahead, 842 // note that the line may be also be considered writable in 843 // downstream caches along the path to memory, but always 844 // Exclusive, and never Modified 845 assert(blk->isWritable()); 846 // Write or WriteLine at the first cache with block in writable state 847 if (blk->checkWrite(pkt)) { 848 pkt->writeDataToBlock(blk->data, blkSize); 849 } 850 // Always mark the line as dirty (and thus transition to the 851 // Modified state) even if we are a failed StoreCond so we 852 // supply data to any snoops that have appended themselves to 853 // this cache before knowing the store will fail. 854 blk->status |= BlkDirty; 855 DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 856 } else if (pkt->isRead()) { 857 if (pkt->isLLSC()) { 858 blk->trackLoadLocked(pkt); 859 } 860 861 // all read responses have a data payload 862 assert(pkt->hasRespData()); 863 pkt->setDataFromBlock(blk->data, blkSize); 864 } else if (pkt->isUpgrade()) { 865 // sanity check 866 assert(!pkt->hasSharers()); 867 868 if (blk->isDirty()) { 869 // we were in the Owned state, and a cache above us that 870 // has the line in Shared state needs to be made aware 871 // that the data it already has is in fact dirty 872 pkt->setCacheResponding(); 873 blk->status &= ~BlkDirty; 874 } 875 } else { 876 assert(pkt->isInvalidate()); 877 invalidateBlock(blk); 878 DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 879 pkt->print()); 880 } 881} 882 883///////////////////////////////////////////////////// 884// 885// Access path: requests coming in from the CPU side 886// 887///////////////////////////////////////////////////// 888 889bool 890BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 891 PacketList &writebacks) 892{ 893 // sanity check 894 assert(pkt->isRequest()); 895 896 chatty_assert(!(isReadOnly && pkt->isWrite()), 897 "Should never see a write in a read-only cache %s\n", 898 name()); 899 900 // Here lat is the value passed as parameter to accessBlock() function 901 // that can modify its value. 902 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 903 904 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 905 blk ? "hit " + blk->print() : "miss"); 906 907 if (pkt->req->isCacheMaintenance()) { 908 // A cache maintenance operation is always forwarded to the 909 // memory below even if the block is found in dirty state. 910 911 // We defer any changes to the state of the block until we 912 // create and mark as in service the mshr for the downstream 913 // packet. 914 return false; 915 } 916 917 if (pkt->isEviction()) { 918 // We check for presence of block in above caches before issuing 919 // Writeback or CleanEvict to write buffer. Therefore the only 920 // possible cases can be of a CleanEvict packet coming from above 921 // encountering a Writeback generated in this cache peer cache and 922 // waiting in the write buffer. Cases of upper level peer caches 923 // generating CleanEvict and Writeback or simply CleanEvict and 924 // CleanEvict almost simultaneously will be caught by snoops sent out 925 // by crossbar. 926 WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 927 pkt->isSecure()); 928 if (wb_entry) { 929 assert(wb_entry->getNumTargets() == 1); 930 PacketPtr wbPkt = wb_entry->getTarget()->pkt; 931 assert(wbPkt->isWriteback()); 932 933 if (pkt->isCleanEviction()) { 934 // The CleanEvict and WritebackClean snoops into other 935 // peer caches of the same level while traversing the 936 // crossbar. If a copy of the block is found, the 937 // packet is deleted in the crossbar. Hence, none of 938 // the other upper level caches connected to this 939 // cache have the block, so we can clear the 940 // BLOCK_CACHED flag in the Writeback if set and 941 // discard the CleanEvict by returning true. 942 wbPkt->clearBlockCached(); 943 return true; 944 } else { 945 assert(pkt->cmd == MemCmd::WritebackDirty); 946 // Dirty writeback from above trumps our clean 947 // writeback... discard here 948 // Note: markInService will remove entry from writeback buffer. 949 markInService(wb_entry); 950 delete wbPkt; 951 } 952 } 953 } 954 955 // Writeback handling is special case. We can write the block into 956 // the cache without having a writeable copy (or any copy at all). 957 if (pkt->isWriteback()) { 958 assert(blkSize == pkt->getSize()); 959 960 // we could get a clean writeback while we are having 961 // outstanding accesses to a block, do the simple thing for 962 // now and drop the clean writeback so that we do not upset 963 // any ordering/decisions about ownership already taken 964 if (pkt->cmd == MemCmd::WritebackClean && 965 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 966 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 967 "dropping\n", pkt->getAddr()); 968 return true; 969 } 970 971 if (!blk) { 972 // need to do a replacement
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1260 return victim; 1261} 1262 1263void 1264BaseCache::invalidateBlock(CacheBlk *blk) 1265{ 1266 if (blk != tempBlock) 1267 tags->invalidate(blk); 1268 blk->invalidate(); 1269} 1270 1271PacketPtr 1272BaseCache::writebackBlk(CacheBlk *blk) 1273{ 1274 chatty_assert(!isReadOnly || writebackClean, 1275 "Writeback from read-only cache"); 1276 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 1277 1278 writebacks[Request::wbMasterId]++; 1279 1280 RequestPtr req = std::make_shared<Request>( 1281 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 1282 1283 if (blk->isSecure()) 1284 req->setFlags(Request::SECURE); 1285 1286 req->taskId(blk->task_id); 1287 1288 PacketPtr pkt = 1289 new Packet(req, blk->isDirty() ? 1290 MemCmd::WritebackDirty : MemCmd::WritebackClean); 1291 1292 DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 1293 pkt->print(), blk->isWritable(), blk->isDirty()); 1294 1295 if (blk->isWritable()) { 1296 // not asserting shared means we pass the block in modified 1297 // state, mark our own block non-writeable 1298 blk->status &= ~BlkWritable; 1299 } else { 1300 // we are in the Owned state, tell the receiver 1301 pkt->setHasSharers(); 1302 } 1303 1304 // make sure the block is not marked dirty 1305 blk->status &= ~BlkDirty; 1306 1307 pkt->allocate(); 1308 pkt->setDataFromBlock(blk->data, blkSize); 1309 1310 return pkt; 1311} 1312 1313PacketPtr 1314BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 1315{ 1316 RequestPtr req = std::make_shared<Request>( 1317 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 1318 1319 if (blk->isSecure()) { 1320 req->setFlags(Request::SECURE); 1321 } 1322 req->taskId(blk->task_id); 1323 1324 PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 1325 1326 if (dest) { 1327 req->setFlags(dest); 1328 pkt->setWriteThrough(); 1329 } 1330 1331 DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 1332 blk->isWritable(), blk->isDirty()); 1333 1334 if (blk->isWritable()) { 1335 // not asserting shared means we pass the block in modified 1336 // state, mark our own block non-writeable 1337 blk->status &= ~BlkWritable; 1338 } else { 1339 // we are in the Owned state, tell the receiver 1340 pkt->setHasSharers(); 1341 } 1342 1343 // make sure the block is not marked dirty 1344 blk->status &= ~BlkDirty; 1345 1346 pkt->allocate(); 1347 pkt->setDataFromBlock(blk->data, blkSize); 1348 1349 return pkt; 1350} 1351 1352 1353void 1354BaseCache::memWriteback() 1355{ 1356 tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); 1357} 1358 1359void 1360BaseCache::memInvalidate() 1361{ 1362 tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); 1363} 1364 1365bool 1366BaseCache::isDirty() const 1367{ 1368 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); 1369} 1370 1371void 1372BaseCache::writebackVisitor(CacheBlk &blk) 1373{ 1374 if (blk.isDirty()) { 1375 assert(blk.isValid()); 1376 1377 RequestPtr request = std::make_shared<Request>( 1378 regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); 1379 1380 request->taskId(blk.task_id); 1381 if (blk.isSecure()) { 1382 request->setFlags(Request::SECURE); 1383 } 1384 1385 Packet packet(request, MemCmd::WriteReq); 1386 packet.dataStatic(blk.data); 1387 1388 memSidePort.sendFunctional(&packet); 1389 1390 blk.status &= ~BlkDirty; 1391 } 1392} 1393 1394void 1395BaseCache::invalidateVisitor(CacheBlk &blk) 1396{ 1397 if (blk.isDirty()) 1398 warn_once("Invalidating dirty cache lines. " \ 1399 "Expect things to break.\n"); 1400 1401 if (blk.isValid()) { 1402 assert(!blk.isDirty()); 1403 invalidateBlock(&blk); 1404 } 1405} 1406 1407Tick 1408BaseCache::nextQueueReadyTime() const 1409{ 1410 Tick nextReady = std::min(mshrQueue.nextReadyTime(), 1411 writeBuffer.nextReadyTime()); 1412 1413 // Don't signal prefetch ready time if no MSHRs available 1414 // Will signal once enoguh MSHRs are deallocated 1415 if (prefetcher && mshrQueue.canPrefetch()) { 1416 nextReady = std::min(nextReady, 1417 prefetcher->nextPrefetchReadyTime()); 1418 } 1419 1420 return nextReady; 1421} 1422 1423 1424bool 1425BaseCache::sendMSHRQueuePacket(MSHR* mshr) 1426{ 1427 assert(mshr); 1428 1429 // use request from 1st target 1430 PacketPtr tgt_pkt = mshr->getTarget()->pkt; 1431 1432 DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 1433 1434 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 1435 1436 // either a prefetch that is not present upstream, or a normal 1437 // MSHR request, proceed to get the packet to send downstream 1438 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 1439 1440 mshr->isForward = (pkt == nullptr); 1441 1442 if (mshr->isForward) { 1443 // not a cache block request, but a response is expected 1444 // make copy of current packet to forward, keep current 1445 // copy for response handling 1446 pkt = new Packet(tgt_pkt, false, true); 1447 assert(!pkt->isWrite()); 1448 } 1449 1450 // play it safe and append (rather than set) the sender state, 1451 // as forwarded packets may already have existing state 1452 pkt->pushSenderState(mshr); 1453 1454 if (pkt->isClean() && blk && blk->isDirty()) { 1455 // A cache clean opearation is looking for a dirty block. Mark 1456 // the packet so that the destination xbar can determine that 1457 // there will be a follow-up write packet as well. 1458 pkt->setSatisfied(); 1459 } 1460 1461 if (!memSidePort.sendTimingReq(pkt)) { 1462 // we are awaiting a retry, but we 1463 // delete the packet and will be creating a new packet 1464 // when we get the opportunity 1465 delete pkt; 1466 1467 // note that we have now masked any requestBus and 1468 // schedSendEvent (we will wait for a retry before 1469 // doing anything), and this is so even if we do not 1470 // care about this packet and might override it before 1471 // it gets retried 1472 return true; 1473 } else { 1474 // As part of the call to sendTimingReq the packet is 1475 // forwarded to all neighbouring caches (and any caches 1476 // above them) as a snoop. Thus at this point we know if 1477 // any of the neighbouring caches are responding, and if 1478 // so, we know it is dirty, and we can determine if it is 1479 // being passed as Modified, making our MSHR the ordering 1480 // point 1481 bool pending_modified_resp = !pkt->hasSharers() && 1482 pkt->cacheResponding(); 1483 markInService(mshr, pending_modified_resp); 1484 1485 if (pkt->isClean() && blk && blk->isDirty()) { 1486 // A cache clean opearation is looking for a dirty 1487 // block. If a dirty block is encountered a WriteClean 1488 // will update any copies to the path to the memory 1489 // until the point of reference. 1490 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 1491 __func__, pkt->print(), blk->print()); 1492 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 1493 pkt->id); 1494 PacketList writebacks; 1495 writebacks.push_back(wb_pkt); 1496 doWritebacks(writebacks, 0); 1497 } 1498 1499 return false; 1500 } 1501} 1502 1503bool 1504BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 1505{ 1506 assert(wq_entry); 1507 1508 // always a single target for write queue entries 1509 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 1510 1511 DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 1512 1513 // forward as is, both for evictions and uncacheable writes 1514 if (!memSidePort.sendTimingReq(tgt_pkt)) { 1515 // note that we have now masked any requestBus and 1516 // schedSendEvent (we will wait for a retry before 1517 // doing anything), and this is so even if we do not 1518 // care about this packet and might override it before 1519 // it gets retried 1520 return true; 1521 } else { 1522 markInService(wq_entry); 1523 return false; 1524 } 1525} 1526 1527void 1528BaseCache::serialize(CheckpointOut &cp) const 1529{ 1530 bool dirty(isDirty()); 1531 1532 if (dirty) { 1533 warn("*** The cache still contains dirty data. ***\n"); 1534 warn(" Make sure to drain the system using the correct flags.\n"); 1535 warn(" This checkpoint will not restore correctly " \ 1536 "and dirty data in the cache will be lost!\n"); 1537 } 1538 1539 // Since we don't checkpoint the data in the cache, any dirty data 1540 // will be lost when restoring from a checkpoint of a system that 1541 // wasn't drained properly. Flag the checkpoint as invalid if the 1542 // cache contains dirty data. 1543 bool bad_checkpoint(dirty); 1544 SERIALIZE_SCALAR(bad_checkpoint); 1545} 1546 1547void 1548BaseCache::unserialize(CheckpointIn &cp) 1549{ 1550 bool bad_checkpoint; 1551 UNSERIALIZE_SCALAR(bad_checkpoint); 1552 if (bad_checkpoint) { 1553 fatal("Restoring from checkpoints with dirty caches is not " 1554 "supported in the classic memory system. Please remove any " 1555 "caches or drain them properly before taking checkpoints.\n"); 1556 } 1557} 1558 1559void 1560BaseCache::regStats() 1561{ 1562 MemObject::regStats(); 1563 1564 using namespace Stats; 1565 1566 // Hit statistics 1567 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1568 MemCmd cmd(access_idx); 1569 const string &cstr = cmd.toString(); 1570 1571 hits[access_idx] 1572 .init(system->maxMasters()) 1573 .name(name() + "." + cstr + "_hits") 1574 .desc("number of " + cstr + " hits") 1575 .flags(total | nozero | nonan) 1576 ; 1577 for (int i = 0; i < system->maxMasters(); i++) { 1578 hits[access_idx].subname(i, system->getMasterName(i)); 1579 } 1580 } 1581 1582// These macros make it easier to sum the right subset of commands and 1583// to change the subset of commands that are considered "demand" vs 1584// "non-demand" 1585#define SUM_DEMAND(s) \ 1586 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 1587 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 1588 1589// should writebacks be included here? prior code was inconsistent... 1590#define SUM_NON_DEMAND(s) \ 1591 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1592 1593 demandHits 1594 .name(name() + ".demand_hits") 1595 .desc("number of demand (read+write) hits") 1596 .flags(total | nozero | nonan) 1597 ; 1598 demandHits = SUM_DEMAND(hits); 1599 for (int i = 0; i < system->maxMasters(); i++) { 1600 demandHits.subname(i, system->getMasterName(i)); 1601 } 1602 1603 overallHits 1604 .name(name() + ".overall_hits") 1605 .desc("number of overall hits") 1606 .flags(total | nozero | nonan) 1607 ; 1608 overallHits = demandHits + SUM_NON_DEMAND(hits); 1609 for (int i = 0; i < system->maxMasters(); i++) { 1610 overallHits.subname(i, system->getMasterName(i)); 1611 } 1612 1613 // Miss statistics 1614 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1615 MemCmd cmd(access_idx); 1616 const string &cstr = cmd.toString(); 1617 1618 misses[access_idx] 1619 .init(system->maxMasters()) 1620 .name(name() + "." + cstr + "_misses") 1621 .desc("number of " + cstr + " misses") 1622 .flags(total | nozero | nonan) 1623 ; 1624 for (int i = 0; i < system->maxMasters(); i++) { 1625 misses[access_idx].subname(i, system->getMasterName(i)); 1626 } 1627 } 1628 1629 demandMisses 1630 .name(name() + ".demand_misses") 1631 .desc("number of demand (read+write) misses") 1632 .flags(total | nozero | nonan) 1633 ; 1634 demandMisses = SUM_DEMAND(misses); 1635 for (int i = 0; i < system->maxMasters(); i++) { 1636 demandMisses.subname(i, system->getMasterName(i)); 1637 } 1638 1639 overallMisses 1640 .name(name() + ".overall_misses") 1641 .desc("number of overall misses") 1642 .flags(total | nozero | nonan) 1643 ; 1644 overallMisses = demandMisses + SUM_NON_DEMAND(misses); 1645 for (int i = 0; i < system->maxMasters(); i++) { 1646 overallMisses.subname(i, system->getMasterName(i)); 1647 } 1648 1649 // Miss latency statistics 1650 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1651 MemCmd cmd(access_idx); 1652 const string &cstr = cmd.toString(); 1653 1654 missLatency[access_idx] 1655 .init(system->maxMasters()) 1656 .name(name() + "." + cstr + "_miss_latency") 1657 .desc("number of " + cstr + " miss cycles") 1658 .flags(total | nozero | nonan) 1659 ; 1660 for (int i = 0; i < system->maxMasters(); i++) { 1661 missLatency[access_idx].subname(i, system->getMasterName(i)); 1662 } 1663 } 1664 1665 demandMissLatency 1666 .name(name() + ".demand_miss_latency") 1667 .desc("number of demand (read+write) miss cycles") 1668 .flags(total | nozero | nonan) 1669 ; 1670 demandMissLatency = SUM_DEMAND(missLatency); 1671 for (int i = 0; i < system->maxMasters(); i++) { 1672 demandMissLatency.subname(i, system->getMasterName(i)); 1673 } 1674 1675 overallMissLatency 1676 .name(name() + ".overall_miss_latency") 1677 .desc("number of overall miss cycles") 1678 .flags(total | nozero | nonan) 1679 ; 1680 overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 1681 for (int i = 0; i < system->maxMasters(); i++) { 1682 overallMissLatency.subname(i, system->getMasterName(i)); 1683 } 1684 1685 // access formulas 1686 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1687 MemCmd cmd(access_idx); 1688 const string &cstr = cmd.toString(); 1689 1690 accesses[access_idx] 1691 .name(name() + "." + cstr + "_accesses") 1692 .desc("number of " + cstr + " accesses(hits+misses)") 1693 .flags(total | nozero | nonan) 1694 ; 1695 accesses[access_idx] = hits[access_idx] + misses[access_idx]; 1696 1697 for (int i = 0; i < system->maxMasters(); i++) { 1698 accesses[access_idx].subname(i, system->getMasterName(i)); 1699 } 1700 } 1701 1702 demandAccesses 1703 .name(name() + ".demand_accesses") 1704 .desc("number of demand (read+write) accesses") 1705 .flags(total | nozero | nonan) 1706 ; 1707 demandAccesses = demandHits + demandMisses; 1708 for (int i = 0; i < system->maxMasters(); i++) { 1709 demandAccesses.subname(i, system->getMasterName(i)); 1710 } 1711 1712 overallAccesses 1713 .name(name() + ".overall_accesses") 1714 .desc("number of overall (read+write) accesses") 1715 .flags(total | nozero | nonan) 1716 ; 1717 overallAccesses = overallHits + overallMisses; 1718 for (int i = 0; i < system->maxMasters(); i++) { 1719 overallAccesses.subname(i, system->getMasterName(i)); 1720 } 1721 1722 // miss rate formulas 1723 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1724 MemCmd cmd(access_idx); 1725 const string &cstr = cmd.toString(); 1726 1727 missRate[access_idx] 1728 .name(name() + "." + cstr + "_miss_rate") 1729 .desc("miss rate for " + cstr + " accesses") 1730 .flags(total | nozero | nonan) 1731 ; 1732 missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 1733 1734 for (int i = 0; i < system->maxMasters(); i++) { 1735 missRate[access_idx].subname(i, system->getMasterName(i)); 1736 } 1737 } 1738 1739 demandMissRate 1740 .name(name() + ".demand_miss_rate") 1741 .desc("miss rate for demand accesses") 1742 .flags(total | nozero | nonan) 1743 ; 1744 demandMissRate = demandMisses / demandAccesses; 1745 for (int i = 0; i < system->maxMasters(); i++) { 1746 demandMissRate.subname(i, system->getMasterName(i)); 1747 } 1748 1749 overallMissRate 1750 .name(name() + ".overall_miss_rate") 1751 .desc("miss rate for overall accesses") 1752 .flags(total | nozero | nonan) 1753 ; 1754 overallMissRate = overallMisses / overallAccesses; 1755 for (int i = 0; i < system->maxMasters(); i++) { 1756 overallMissRate.subname(i, system->getMasterName(i)); 1757 } 1758 1759 // miss latency formulas 1760 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1761 MemCmd cmd(access_idx); 1762 const string &cstr = cmd.toString(); 1763 1764 avgMissLatency[access_idx] 1765 .name(name() + "." + cstr + "_avg_miss_latency") 1766 .desc("average " + cstr + " miss latency") 1767 .flags(total | nozero | nonan) 1768 ; 1769 avgMissLatency[access_idx] = 1770 missLatency[access_idx] / misses[access_idx]; 1771 1772 for (int i = 0; i < system->maxMasters(); i++) { 1773 avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 1774 } 1775 } 1776 1777 demandAvgMissLatency 1778 .name(name() + ".demand_avg_miss_latency") 1779 .desc("average overall miss latency") 1780 .flags(total | nozero | nonan) 1781 ; 1782 demandAvgMissLatency = demandMissLatency / demandMisses; 1783 for (int i = 0; i < system->maxMasters(); i++) { 1784 demandAvgMissLatency.subname(i, system->getMasterName(i)); 1785 } 1786 1787 overallAvgMissLatency 1788 .name(name() + ".overall_avg_miss_latency") 1789 .desc("average overall miss latency") 1790 .flags(total | nozero | nonan) 1791 ; 1792 overallAvgMissLatency = overallMissLatency / overallMisses; 1793 for (int i = 0; i < system->maxMasters(); i++) { 1794 overallAvgMissLatency.subname(i, system->getMasterName(i)); 1795 } 1796 1797 blocked_cycles.init(NUM_BLOCKED_CAUSES); 1798 blocked_cycles 1799 .name(name() + ".blocked_cycles") 1800 .desc("number of cycles access was blocked") 1801 .subname(Blocked_NoMSHRs, "no_mshrs") 1802 .subname(Blocked_NoTargets, "no_targets") 1803 ; 1804 1805 1806 blocked_causes.init(NUM_BLOCKED_CAUSES); 1807 blocked_causes 1808 .name(name() + ".blocked") 1809 .desc("number of cycles access was blocked") 1810 .subname(Blocked_NoMSHRs, "no_mshrs") 1811 .subname(Blocked_NoTargets, "no_targets") 1812 ; 1813 1814 avg_blocked 1815 .name(name() + ".avg_blocked_cycles") 1816 .desc("average number of cycles each access was blocked") 1817 .subname(Blocked_NoMSHRs, "no_mshrs") 1818 .subname(Blocked_NoTargets, "no_targets") 1819 ; 1820 1821 avg_blocked = blocked_cycles / blocked_causes; 1822 1823 unusedPrefetches 1824 .name(name() + ".unused_prefetches") 1825 .desc("number of HardPF blocks evicted w/o reference") 1826 .flags(nozero) 1827 ; 1828 1829 writebacks 1830 .init(system->maxMasters()) 1831 .name(name() + ".writebacks") 1832 .desc("number of writebacks") 1833 .flags(total | nozero | nonan) 1834 ; 1835 for (int i = 0; i < system->maxMasters(); i++) { 1836 writebacks.subname(i, system->getMasterName(i)); 1837 } 1838 1839 // MSHR statistics 1840 // MSHR hit statistics 1841 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1842 MemCmd cmd(access_idx); 1843 const string &cstr = cmd.toString(); 1844 1845 mshr_hits[access_idx] 1846 .init(system->maxMasters()) 1847 .name(name() + "." + cstr + "_mshr_hits") 1848 .desc("number of " + cstr + " MSHR hits") 1849 .flags(total | nozero | nonan) 1850 ; 1851 for (int i = 0; i < system->maxMasters(); i++) { 1852 mshr_hits[access_idx].subname(i, system->getMasterName(i)); 1853 } 1854 } 1855 1856 demandMshrHits 1857 .name(name() + ".demand_mshr_hits") 1858 .desc("number of demand (read+write) MSHR hits") 1859 .flags(total | nozero | nonan) 1860 ; 1861 demandMshrHits = SUM_DEMAND(mshr_hits); 1862 for (int i = 0; i < system->maxMasters(); i++) { 1863 demandMshrHits.subname(i, system->getMasterName(i)); 1864 } 1865 1866 overallMshrHits 1867 .name(name() + ".overall_mshr_hits") 1868 .desc("number of overall MSHR hits") 1869 .flags(total | nozero | nonan) 1870 ; 1871 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 1872 for (int i = 0; i < system->maxMasters(); i++) { 1873 overallMshrHits.subname(i, system->getMasterName(i)); 1874 } 1875 1876 // MSHR miss statistics 1877 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1878 MemCmd cmd(access_idx); 1879 const string &cstr = cmd.toString(); 1880 1881 mshr_misses[access_idx] 1882 .init(system->maxMasters()) 1883 .name(name() + "." + cstr + "_mshr_misses") 1884 .desc("number of " + cstr + " MSHR misses") 1885 .flags(total | nozero | nonan) 1886 ; 1887 for (int i = 0; i < system->maxMasters(); i++) { 1888 mshr_misses[access_idx].subname(i, system->getMasterName(i)); 1889 } 1890 } 1891 1892 demandMshrMisses 1893 .name(name() + ".demand_mshr_misses") 1894 .desc("number of demand (read+write) MSHR misses") 1895 .flags(total | nozero | nonan) 1896 ; 1897 demandMshrMisses = SUM_DEMAND(mshr_misses); 1898 for (int i = 0; i < system->maxMasters(); i++) { 1899 demandMshrMisses.subname(i, system->getMasterName(i)); 1900 } 1901 1902 overallMshrMisses 1903 .name(name() + ".overall_mshr_misses") 1904 .desc("number of overall MSHR misses") 1905 .flags(total | nozero | nonan) 1906 ; 1907 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 1908 for (int i = 0; i < system->maxMasters(); i++) { 1909 overallMshrMisses.subname(i, system->getMasterName(i)); 1910 } 1911 1912 // MSHR miss latency statistics 1913 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1914 MemCmd cmd(access_idx); 1915 const string &cstr = cmd.toString(); 1916 1917 mshr_miss_latency[access_idx] 1918 .init(system->maxMasters()) 1919 .name(name() + "." + cstr + "_mshr_miss_latency") 1920 .desc("number of " + cstr + " MSHR miss cycles") 1921 .flags(total | nozero | nonan) 1922 ; 1923 for (int i = 0; i < system->maxMasters(); i++) { 1924 mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 1925 } 1926 } 1927 1928 demandMshrMissLatency 1929 .name(name() + ".demand_mshr_miss_latency") 1930 .desc("number of demand (read+write) MSHR miss cycles") 1931 .flags(total | nozero | nonan) 1932 ; 1933 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 1934 for (int i = 0; i < system->maxMasters(); i++) { 1935 demandMshrMissLatency.subname(i, system->getMasterName(i)); 1936 } 1937 1938 overallMshrMissLatency 1939 .name(name() + ".overall_mshr_miss_latency") 1940 .desc("number of overall MSHR miss cycles") 1941 .flags(total | nozero | nonan) 1942 ; 1943 overallMshrMissLatency = 1944 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 1945 for (int i = 0; i < system->maxMasters(); i++) { 1946 overallMshrMissLatency.subname(i, system->getMasterName(i)); 1947 } 1948 1949 // MSHR uncacheable statistics 1950 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1951 MemCmd cmd(access_idx); 1952 const string &cstr = cmd.toString(); 1953 1954 mshr_uncacheable[access_idx] 1955 .init(system->maxMasters()) 1956 .name(name() + "." + cstr + "_mshr_uncacheable") 1957 .desc("number of " + cstr + " MSHR uncacheable") 1958 .flags(total | nozero | nonan) 1959 ; 1960 for (int i = 0; i < system->maxMasters(); i++) { 1961 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 1962 } 1963 } 1964 1965 overallMshrUncacheable 1966 .name(name() + ".overall_mshr_uncacheable_misses") 1967 .desc("number of overall MSHR uncacheable misses") 1968 .flags(total | nozero | nonan) 1969 ; 1970 overallMshrUncacheable = 1971 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 1972 for (int i = 0; i < system->maxMasters(); i++) { 1973 overallMshrUncacheable.subname(i, system->getMasterName(i)); 1974 } 1975 1976 // MSHR miss latency statistics 1977 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1978 MemCmd cmd(access_idx); 1979 const string &cstr = cmd.toString(); 1980 1981 mshr_uncacheable_lat[access_idx] 1982 .init(system->maxMasters()) 1983 .name(name() + "." + cstr + "_mshr_uncacheable_latency") 1984 .desc("number of " + cstr + " MSHR uncacheable cycles") 1985 .flags(total | nozero | nonan) 1986 ; 1987 for (int i = 0; i < system->maxMasters(); i++) { 1988 mshr_uncacheable_lat[access_idx].subname( 1989 i, system->getMasterName(i)); 1990 } 1991 } 1992 1993 overallMshrUncacheableLatency 1994 .name(name() + ".overall_mshr_uncacheable_latency") 1995 .desc("number of overall MSHR uncacheable cycles") 1996 .flags(total | nozero | nonan) 1997 ; 1998 overallMshrUncacheableLatency = 1999 SUM_DEMAND(mshr_uncacheable_lat) + 2000 SUM_NON_DEMAND(mshr_uncacheable_lat); 2001 for (int i = 0; i < system->maxMasters(); i++) { 2002 overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 2003 } 2004 2005#if 0 2006 // MSHR access formulas 2007 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2008 MemCmd cmd(access_idx); 2009 const string &cstr = cmd.toString(); 2010 2011 mshrAccesses[access_idx] 2012 .name(name() + "." + cstr + "_mshr_accesses") 2013 .desc("number of " + cstr + " mshr accesses(hits+misses)") 2014 .flags(total | nozero | nonan) 2015 ; 2016 mshrAccesses[access_idx] = 2017 mshr_hits[access_idx] + mshr_misses[access_idx] 2018 + mshr_uncacheable[access_idx]; 2019 } 2020 2021 demandMshrAccesses 2022 .name(name() + ".demand_mshr_accesses") 2023 .desc("number of demand (read+write) mshr accesses") 2024 .flags(total | nozero | nonan) 2025 ; 2026 demandMshrAccesses = demandMshrHits + demandMshrMisses; 2027 2028 overallMshrAccesses 2029 .name(name() + ".overall_mshr_accesses") 2030 .desc("number of overall (read+write) mshr accesses") 2031 .flags(total | nozero | nonan) 2032 ; 2033 overallMshrAccesses = overallMshrHits + overallMshrMisses 2034 + overallMshrUncacheable; 2035#endif 2036 2037 // MSHR miss rate formulas 2038 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2039 MemCmd cmd(access_idx); 2040 const string &cstr = cmd.toString(); 2041 2042 mshrMissRate[access_idx] 2043 .name(name() + "." + cstr + "_mshr_miss_rate") 2044 .desc("mshr miss rate for " + cstr + " accesses") 2045 .flags(total | nozero | nonan) 2046 ; 2047 mshrMissRate[access_idx] = 2048 mshr_misses[access_idx] / accesses[access_idx]; 2049 2050 for (int i = 0; i < system->maxMasters(); i++) { 2051 mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 2052 } 2053 } 2054 2055 demandMshrMissRate 2056 .name(name() + ".demand_mshr_miss_rate") 2057 .desc("mshr miss rate for demand accesses") 2058 .flags(total | nozero | nonan) 2059 ; 2060 demandMshrMissRate = demandMshrMisses / demandAccesses; 2061 for (int i = 0; i < system->maxMasters(); i++) { 2062 demandMshrMissRate.subname(i, system->getMasterName(i)); 2063 } 2064 2065 overallMshrMissRate 2066 .name(name() + ".overall_mshr_miss_rate") 2067 .desc("mshr miss rate for overall accesses") 2068 .flags(total | nozero | nonan) 2069 ; 2070 overallMshrMissRate = overallMshrMisses / overallAccesses; 2071 for (int i = 0; i < system->maxMasters(); i++) { 2072 overallMshrMissRate.subname(i, system->getMasterName(i)); 2073 } 2074 2075 // mshrMiss latency formulas 2076 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2077 MemCmd cmd(access_idx); 2078 const string &cstr = cmd.toString(); 2079 2080 avgMshrMissLatency[access_idx] 2081 .name(name() + "." + cstr + "_avg_mshr_miss_latency") 2082 .desc("average " + cstr + " mshr miss latency") 2083 .flags(total | nozero | nonan) 2084 ; 2085 avgMshrMissLatency[access_idx] = 2086 mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 2087 2088 for (int i = 0; i < system->maxMasters(); i++) { 2089 avgMshrMissLatency[access_idx].subname( 2090 i, system->getMasterName(i)); 2091 } 2092 } 2093 2094 demandAvgMshrMissLatency 2095 .name(name() + ".demand_avg_mshr_miss_latency") 2096 .desc("average overall mshr miss latency") 2097 .flags(total | nozero | nonan) 2098 ; 2099 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 2100 for (int i = 0; i < system->maxMasters(); i++) { 2101 demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 2102 } 2103 2104 overallAvgMshrMissLatency 2105 .name(name() + ".overall_avg_mshr_miss_latency") 2106 .desc("average overall mshr miss latency") 2107 .flags(total | nozero | nonan) 2108 ; 2109 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 2110 for (int i = 0; i < system->maxMasters(); i++) { 2111 overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 2112 } 2113 2114 // mshrUncacheable latency formulas 2115 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2116 MemCmd cmd(access_idx); 2117 const string &cstr = cmd.toString(); 2118 2119 avgMshrUncacheableLatency[access_idx] 2120 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 2121 .desc("average " + cstr + " mshr uncacheable latency") 2122 .flags(total | nozero | nonan) 2123 ; 2124 avgMshrUncacheableLatency[access_idx] = 2125 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 2126 2127 for (int i = 0; i < system->maxMasters(); i++) { 2128 avgMshrUncacheableLatency[access_idx].subname( 2129 i, system->getMasterName(i)); 2130 } 2131 } 2132 2133 overallAvgMshrUncacheableLatency 2134 .name(name() + ".overall_avg_mshr_uncacheable_latency") 2135 .desc("average overall mshr uncacheable latency") 2136 .flags(total | nozero | nonan) 2137 ; 2138 overallAvgMshrUncacheableLatency = 2139 overallMshrUncacheableLatency / overallMshrUncacheable; 2140 for (int i = 0; i < system->maxMasters(); i++) { 2141 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 2142 } 2143 2144 replacements 2145 .name(name() + ".replacements") 2146 .desc("number of replacements") 2147 ; 2148} 2149 2150/////////////// 2151// 2152// CpuSidePort 2153// 2154/////////////// 2155bool 2156BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 2157{ 2158 // Snoops shouldn't happen when bypassing caches 2159 assert(!cache->system->bypassCaches()); 2160 2161 assert(pkt->isResponse()); 2162 2163 // Express snoop responses from master to slave, e.g., from L1 to L2 2164 cache->recvTimingSnoopResp(pkt); 2165 return true; 2166} 2167 2168 2169bool 2170BaseCache::CpuSidePort::tryTiming(PacketPtr pkt) 2171{ 2172 if (cache->system->bypassCaches() || pkt->isExpressSnoop()) { 2173 // always let express snoop packets through even if blocked 2174 return true; 2175 } else if (blocked || mustSendRetry) { 2176 // either already committed to send a retry, or blocked 2177 mustSendRetry = true; 2178 return false; 2179 } 2180 mustSendRetry = false; 2181 return true; 2182} 2183 2184bool 2185BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 2186{ 2187 assert(pkt->isRequest()); 2188 2189 if (cache->system->bypassCaches()) { 2190 // Just forward the packet if caches are disabled. 2191 // @todo This should really enqueue the packet rather 2192 bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt); 2193 assert(success); 2194 return true; 2195 } else if (tryTiming(pkt)) { 2196 cache->recvTimingReq(pkt); 2197 return true; 2198 } 2199 return false; 2200} 2201 2202Tick 2203BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt) 2204{ 2205 if (cache->system->bypassCaches()) { 2206 // Forward the request if the system is in cache bypass mode. 2207 return cache->memSidePort.sendAtomic(pkt); 2208 } else { 2209 return cache->recvAtomic(pkt); 2210 } 2211} 2212 2213void 2214BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt) 2215{ 2216 if (cache->system->bypassCaches()) { 2217 // The cache should be flushed if we are in cache bypass mode, 2218 // so we don't need to check if we need to update anything. 2219 cache->memSidePort.sendFunctional(pkt); 2220 return; 2221 } 2222 2223 // functional request 2224 cache->functionalAccess(pkt, true); 2225} 2226 2227AddrRangeList 2228BaseCache::CpuSidePort::getAddrRanges() const 2229{ 2230 return cache->getAddrRanges(); 2231} 2232 2233 2234BaseCache:: 2235CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache, 2236 const std::string &_label) 2237 : CacheSlavePort(_name, _cache, _label), cache(_cache) 2238{ 2239} 2240 2241/////////////// 2242// 2243// MemSidePort 2244// 2245/////////////// 2246bool 2247BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 2248{ 2249 cache->recvTimingResp(pkt); 2250 return true; 2251} 2252 2253// Express snooping requests to memside port 2254void 2255BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 2256{ 2257 // Snoops shouldn't happen when bypassing caches 2258 assert(!cache->system->bypassCaches()); 2259 2260 // handle snooping requests 2261 cache->recvTimingSnoopReq(pkt); 2262} 2263 2264Tick 2265BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 2266{ 2267 // Snoops shouldn't happen when bypassing caches 2268 assert(!cache->system->bypassCaches()); 2269 2270 return cache->recvAtomicSnoop(pkt); 2271} 2272 2273void 2274BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 2275{ 2276 // Snoops shouldn't happen when bypassing caches 2277 assert(!cache->system->bypassCaches()); 2278 2279 // functional snoop (note that in contrast to atomic we don't have 2280 // a specific functionalSnoop method, as they have the same 2281 // behaviour regardless) 2282 cache->functionalAccess(pkt, false); 2283} 2284 2285void 2286BaseCache::CacheReqPacketQueue::sendDeferredPacket() 2287{ 2288 // sanity check 2289 assert(!waitingOnRetry); 2290 2291 // there should never be any deferred request packets in the 2292 // queue, instead we resly on the cache to provide the packets 2293 // from the MSHR queue or write queue 2294 assert(deferredPacketReadyTime() == MaxTick); 2295 2296 // check for request packets (requests & writebacks) 2297 QueueEntry* entry = cache.getNextQueueEntry(); 2298 2299 if (!entry) { 2300 // can happen if e.g. we attempt a writeback and fail, but 2301 // before the retry, the writeback is eliminated because 2302 // we snoop another cache's ReadEx. 2303 } else { 2304 // let our snoop responses go first if there are responses to 2305 // the same addresses 2306 if (checkConflictingSnoop(entry->blkAddr)) { 2307 return; 2308 } 2309 waitingOnRetry = entry->sendPacket(cache); 2310 } 2311 2312 // if we succeeded and are not waiting for a retry, schedule the 2313 // next send considering when the next queue is ready, note that 2314 // snoop responses have their own packet queue and thus schedule 2315 // their own events 2316 if (!waitingOnRetry) { 2317 schedSendEvent(cache.nextQueueReadyTime()); 2318 } 2319} 2320 2321BaseCache::MemSidePort::MemSidePort(const std::string &_name, 2322 BaseCache *_cache, 2323 const std::string &_label) 2324 : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 2325 _reqQueue(*_cache, *this, _snoopRespQueue, _label), 2326 _snoopRespQueue(*_cache, *this, _label), cache(_cache) 2327{ 2328}
| 1264 return victim; 1265} 1266 1267void 1268BaseCache::invalidateBlock(CacheBlk *blk) 1269{ 1270 if (blk != tempBlock) 1271 tags->invalidate(blk); 1272 blk->invalidate(); 1273} 1274 1275PacketPtr 1276BaseCache::writebackBlk(CacheBlk *blk) 1277{ 1278 chatty_assert(!isReadOnly || writebackClean, 1279 "Writeback from read-only cache"); 1280 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 1281 1282 writebacks[Request::wbMasterId]++; 1283 1284 RequestPtr req = std::make_shared<Request>( 1285 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 1286 1287 if (blk->isSecure()) 1288 req->setFlags(Request::SECURE); 1289 1290 req->taskId(blk->task_id); 1291 1292 PacketPtr pkt = 1293 new Packet(req, blk->isDirty() ? 1294 MemCmd::WritebackDirty : MemCmd::WritebackClean); 1295 1296 DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 1297 pkt->print(), blk->isWritable(), blk->isDirty()); 1298 1299 if (blk->isWritable()) { 1300 // not asserting shared means we pass the block in modified 1301 // state, mark our own block non-writeable 1302 blk->status &= ~BlkWritable; 1303 } else { 1304 // we are in the Owned state, tell the receiver 1305 pkt->setHasSharers(); 1306 } 1307 1308 // make sure the block is not marked dirty 1309 blk->status &= ~BlkDirty; 1310 1311 pkt->allocate(); 1312 pkt->setDataFromBlock(blk->data, blkSize); 1313 1314 return pkt; 1315} 1316 1317PacketPtr 1318BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 1319{ 1320 RequestPtr req = std::make_shared<Request>( 1321 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 1322 1323 if (blk->isSecure()) { 1324 req->setFlags(Request::SECURE); 1325 } 1326 req->taskId(blk->task_id); 1327 1328 PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 1329 1330 if (dest) { 1331 req->setFlags(dest); 1332 pkt->setWriteThrough(); 1333 } 1334 1335 DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 1336 blk->isWritable(), blk->isDirty()); 1337 1338 if (blk->isWritable()) { 1339 // not asserting shared means we pass the block in modified 1340 // state, mark our own block non-writeable 1341 blk->status &= ~BlkWritable; 1342 } else { 1343 // we are in the Owned state, tell the receiver 1344 pkt->setHasSharers(); 1345 } 1346 1347 // make sure the block is not marked dirty 1348 blk->status &= ~BlkDirty; 1349 1350 pkt->allocate(); 1351 pkt->setDataFromBlock(blk->data, blkSize); 1352 1353 return pkt; 1354} 1355 1356 1357void 1358BaseCache::memWriteback() 1359{ 1360 tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); 1361} 1362 1363void 1364BaseCache::memInvalidate() 1365{ 1366 tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); 1367} 1368 1369bool 1370BaseCache::isDirty() const 1371{ 1372 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); 1373} 1374 1375void 1376BaseCache::writebackVisitor(CacheBlk &blk) 1377{ 1378 if (blk.isDirty()) { 1379 assert(blk.isValid()); 1380 1381 RequestPtr request = std::make_shared<Request>( 1382 regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); 1383 1384 request->taskId(blk.task_id); 1385 if (blk.isSecure()) { 1386 request->setFlags(Request::SECURE); 1387 } 1388 1389 Packet packet(request, MemCmd::WriteReq); 1390 packet.dataStatic(blk.data); 1391 1392 memSidePort.sendFunctional(&packet); 1393 1394 blk.status &= ~BlkDirty; 1395 } 1396} 1397 1398void 1399BaseCache::invalidateVisitor(CacheBlk &blk) 1400{ 1401 if (blk.isDirty()) 1402 warn_once("Invalidating dirty cache lines. " \ 1403 "Expect things to break.\n"); 1404 1405 if (blk.isValid()) { 1406 assert(!blk.isDirty()); 1407 invalidateBlock(&blk); 1408 } 1409} 1410 1411Tick 1412BaseCache::nextQueueReadyTime() const 1413{ 1414 Tick nextReady = std::min(mshrQueue.nextReadyTime(), 1415 writeBuffer.nextReadyTime()); 1416 1417 // Don't signal prefetch ready time if no MSHRs available 1418 // Will signal once enoguh MSHRs are deallocated 1419 if (prefetcher && mshrQueue.canPrefetch()) { 1420 nextReady = std::min(nextReady, 1421 prefetcher->nextPrefetchReadyTime()); 1422 } 1423 1424 return nextReady; 1425} 1426 1427 1428bool 1429BaseCache::sendMSHRQueuePacket(MSHR* mshr) 1430{ 1431 assert(mshr); 1432 1433 // use request from 1st target 1434 PacketPtr tgt_pkt = mshr->getTarget()->pkt; 1435 1436 DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 1437 1438 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 1439 1440 // either a prefetch that is not present upstream, or a normal 1441 // MSHR request, proceed to get the packet to send downstream 1442 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 1443 1444 mshr->isForward = (pkt == nullptr); 1445 1446 if (mshr->isForward) { 1447 // not a cache block request, but a response is expected 1448 // make copy of current packet to forward, keep current 1449 // copy for response handling 1450 pkt = new Packet(tgt_pkt, false, true); 1451 assert(!pkt->isWrite()); 1452 } 1453 1454 // play it safe and append (rather than set) the sender state, 1455 // as forwarded packets may already have existing state 1456 pkt->pushSenderState(mshr); 1457 1458 if (pkt->isClean() && blk && blk->isDirty()) { 1459 // A cache clean opearation is looking for a dirty block. Mark 1460 // the packet so that the destination xbar can determine that 1461 // there will be a follow-up write packet as well. 1462 pkt->setSatisfied(); 1463 } 1464 1465 if (!memSidePort.sendTimingReq(pkt)) { 1466 // we are awaiting a retry, but we 1467 // delete the packet and will be creating a new packet 1468 // when we get the opportunity 1469 delete pkt; 1470 1471 // note that we have now masked any requestBus and 1472 // schedSendEvent (we will wait for a retry before 1473 // doing anything), and this is so even if we do not 1474 // care about this packet and might override it before 1475 // it gets retried 1476 return true; 1477 } else { 1478 // As part of the call to sendTimingReq the packet is 1479 // forwarded to all neighbouring caches (and any caches 1480 // above them) as a snoop. Thus at this point we know if 1481 // any of the neighbouring caches are responding, and if 1482 // so, we know it is dirty, and we can determine if it is 1483 // being passed as Modified, making our MSHR the ordering 1484 // point 1485 bool pending_modified_resp = !pkt->hasSharers() && 1486 pkt->cacheResponding(); 1487 markInService(mshr, pending_modified_resp); 1488 1489 if (pkt->isClean() && blk && blk->isDirty()) { 1490 // A cache clean opearation is looking for a dirty 1491 // block. If a dirty block is encountered a WriteClean 1492 // will update any copies to the path to the memory 1493 // until the point of reference. 1494 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 1495 __func__, pkt->print(), blk->print()); 1496 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 1497 pkt->id); 1498 PacketList writebacks; 1499 writebacks.push_back(wb_pkt); 1500 doWritebacks(writebacks, 0); 1501 } 1502 1503 return false; 1504 } 1505} 1506 1507bool 1508BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 1509{ 1510 assert(wq_entry); 1511 1512 // always a single target for write queue entries 1513 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 1514 1515 DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 1516 1517 // forward as is, both for evictions and uncacheable writes 1518 if (!memSidePort.sendTimingReq(tgt_pkt)) { 1519 // note that we have now masked any requestBus and 1520 // schedSendEvent (we will wait for a retry before 1521 // doing anything), and this is so even if we do not 1522 // care about this packet and might override it before 1523 // it gets retried 1524 return true; 1525 } else { 1526 markInService(wq_entry); 1527 return false; 1528 } 1529} 1530 1531void 1532BaseCache::serialize(CheckpointOut &cp) const 1533{ 1534 bool dirty(isDirty()); 1535 1536 if (dirty) { 1537 warn("*** The cache still contains dirty data. ***\n"); 1538 warn(" Make sure to drain the system using the correct flags.\n"); 1539 warn(" This checkpoint will not restore correctly " \ 1540 "and dirty data in the cache will be lost!\n"); 1541 } 1542 1543 // Since we don't checkpoint the data in the cache, any dirty data 1544 // will be lost when restoring from a checkpoint of a system that 1545 // wasn't drained properly. Flag the checkpoint as invalid if the 1546 // cache contains dirty data. 1547 bool bad_checkpoint(dirty); 1548 SERIALIZE_SCALAR(bad_checkpoint); 1549} 1550 1551void 1552BaseCache::unserialize(CheckpointIn &cp) 1553{ 1554 bool bad_checkpoint; 1555 UNSERIALIZE_SCALAR(bad_checkpoint); 1556 if (bad_checkpoint) { 1557 fatal("Restoring from checkpoints with dirty caches is not " 1558 "supported in the classic memory system. Please remove any " 1559 "caches or drain them properly before taking checkpoints.\n"); 1560 } 1561} 1562 1563void 1564BaseCache::regStats() 1565{ 1566 MemObject::regStats(); 1567 1568 using namespace Stats; 1569 1570 // Hit statistics 1571 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1572 MemCmd cmd(access_idx); 1573 const string &cstr = cmd.toString(); 1574 1575 hits[access_idx] 1576 .init(system->maxMasters()) 1577 .name(name() + "." + cstr + "_hits") 1578 .desc("number of " + cstr + " hits") 1579 .flags(total | nozero | nonan) 1580 ; 1581 for (int i = 0; i < system->maxMasters(); i++) { 1582 hits[access_idx].subname(i, system->getMasterName(i)); 1583 } 1584 } 1585 1586// These macros make it easier to sum the right subset of commands and 1587// to change the subset of commands that are considered "demand" vs 1588// "non-demand" 1589#define SUM_DEMAND(s) \ 1590 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 1591 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 1592 1593// should writebacks be included here? prior code was inconsistent... 1594#define SUM_NON_DEMAND(s) \ 1595 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1596 1597 demandHits 1598 .name(name() + ".demand_hits") 1599 .desc("number of demand (read+write) hits") 1600 .flags(total | nozero | nonan) 1601 ; 1602 demandHits = SUM_DEMAND(hits); 1603 for (int i = 0; i < system->maxMasters(); i++) { 1604 demandHits.subname(i, system->getMasterName(i)); 1605 } 1606 1607 overallHits 1608 .name(name() + ".overall_hits") 1609 .desc("number of overall hits") 1610 .flags(total | nozero | nonan) 1611 ; 1612 overallHits = demandHits + SUM_NON_DEMAND(hits); 1613 for (int i = 0; i < system->maxMasters(); i++) { 1614 overallHits.subname(i, system->getMasterName(i)); 1615 } 1616 1617 // Miss statistics 1618 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1619 MemCmd cmd(access_idx); 1620 const string &cstr = cmd.toString(); 1621 1622 misses[access_idx] 1623 .init(system->maxMasters()) 1624 .name(name() + "." + cstr + "_misses") 1625 .desc("number of " + cstr + " misses") 1626 .flags(total | nozero | nonan) 1627 ; 1628 for (int i = 0; i < system->maxMasters(); i++) { 1629 misses[access_idx].subname(i, system->getMasterName(i)); 1630 } 1631 } 1632 1633 demandMisses 1634 .name(name() + ".demand_misses") 1635 .desc("number of demand (read+write) misses") 1636 .flags(total | nozero | nonan) 1637 ; 1638 demandMisses = SUM_DEMAND(misses); 1639 for (int i = 0; i < system->maxMasters(); i++) { 1640 demandMisses.subname(i, system->getMasterName(i)); 1641 } 1642 1643 overallMisses 1644 .name(name() + ".overall_misses") 1645 .desc("number of overall misses") 1646 .flags(total | nozero | nonan) 1647 ; 1648 overallMisses = demandMisses + SUM_NON_DEMAND(misses); 1649 for (int i = 0; i < system->maxMasters(); i++) { 1650 overallMisses.subname(i, system->getMasterName(i)); 1651 } 1652 1653 // Miss latency statistics 1654 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1655 MemCmd cmd(access_idx); 1656 const string &cstr = cmd.toString(); 1657 1658 missLatency[access_idx] 1659 .init(system->maxMasters()) 1660 .name(name() + "." + cstr + "_miss_latency") 1661 .desc("number of " + cstr + " miss cycles") 1662 .flags(total | nozero | nonan) 1663 ; 1664 for (int i = 0; i < system->maxMasters(); i++) { 1665 missLatency[access_idx].subname(i, system->getMasterName(i)); 1666 } 1667 } 1668 1669 demandMissLatency 1670 .name(name() + ".demand_miss_latency") 1671 .desc("number of demand (read+write) miss cycles") 1672 .flags(total | nozero | nonan) 1673 ; 1674 demandMissLatency = SUM_DEMAND(missLatency); 1675 for (int i = 0; i < system->maxMasters(); i++) { 1676 demandMissLatency.subname(i, system->getMasterName(i)); 1677 } 1678 1679 overallMissLatency 1680 .name(name() + ".overall_miss_latency") 1681 .desc("number of overall miss cycles") 1682 .flags(total | nozero | nonan) 1683 ; 1684 overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 1685 for (int i = 0; i < system->maxMasters(); i++) { 1686 overallMissLatency.subname(i, system->getMasterName(i)); 1687 } 1688 1689 // access formulas 1690 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1691 MemCmd cmd(access_idx); 1692 const string &cstr = cmd.toString(); 1693 1694 accesses[access_idx] 1695 .name(name() + "." + cstr + "_accesses") 1696 .desc("number of " + cstr + " accesses(hits+misses)") 1697 .flags(total | nozero | nonan) 1698 ; 1699 accesses[access_idx] = hits[access_idx] + misses[access_idx]; 1700 1701 for (int i = 0; i < system->maxMasters(); i++) { 1702 accesses[access_idx].subname(i, system->getMasterName(i)); 1703 } 1704 } 1705 1706 demandAccesses 1707 .name(name() + ".demand_accesses") 1708 .desc("number of demand (read+write) accesses") 1709 .flags(total | nozero | nonan) 1710 ; 1711 demandAccesses = demandHits + demandMisses; 1712 for (int i = 0; i < system->maxMasters(); i++) { 1713 demandAccesses.subname(i, system->getMasterName(i)); 1714 } 1715 1716 overallAccesses 1717 .name(name() + ".overall_accesses") 1718 .desc("number of overall (read+write) accesses") 1719 .flags(total | nozero | nonan) 1720 ; 1721 overallAccesses = overallHits + overallMisses; 1722 for (int i = 0; i < system->maxMasters(); i++) { 1723 overallAccesses.subname(i, system->getMasterName(i)); 1724 } 1725 1726 // miss rate formulas 1727 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1728 MemCmd cmd(access_idx); 1729 const string &cstr = cmd.toString(); 1730 1731 missRate[access_idx] 1732 .name(name() + "." + cstr + "_miss_rate") 1733 .desc("miss rate for " + cstr + " accesses") 1734 .flags(total | nozero | nonan) 1735 ; 1736 missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 1737 1738 for (int i = 0; i < system->maxMasters(); i++) { 1739 missRate[access_idx].subname(i, system->getMasterName(i)); 1740 } 1741 } 1742 1743 demandMissRate 1744 .name(name() + ".demand_miss_rate") 1745 .desc("miss rate for demand accesses") 1746 .flags(total | nozero | nonan) 1747 ; 1748 demandMissRate = demandMisses / demandAccesses; 1749 for (int i = 0; i < system->maxMasters(); i++) { 1750 demandMissRate.subname(i, system->getMasterName(i)); 1751 } 1752 1753 overallMissRate 1754 .name(name() + ".overall_miss_rate") 1755 .desc("miss rate for overall accesses") 1756 .flags(total | nozero | nonan) 1757 ; 1758 overallMissRate = overallMisses / overallAccesses; 1759 for (int i = 0; i < system->maxMasters(); i++) { 1760 overallMissRate.subname(i, system->getMasterName(i)); 1761 } 1762 1763 // miss latency formulas 1764 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1765 MemCmd cmd(access_idx); 1766 const string &cstr = cmd.toString(); 1767 1768 avgMissLatency[access_idx] 1769 .name(name() + "." + cstr + "_avg_miss_latency") 1770 .desc("average " + cstr + " miss latency") 1771 .flags(total | nozero | nonan) 1772 ; 1773 avgMissLatency[access_idx] = 1774 missLatency[access_idx] / misses[access_idx]; 1775 1776 for (int i = 0; i < system->maxMasters(); i++) { 1777 avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 1778 } 1779 } 1780 1781 demandAvgMissLatency 1782 .name(name() + ".demand_avg_miss_latency") 1783 .desc("average overall miss latency") 1784 .flags(total | nozero | nonan) 1785 ; 1786 demandAvgMissLatency = demandMissLatency / demandMisses; 1787 for (int i = 0; i < system->maxMasters(); i++) { 1788 demandAvgMissLatency.subname(i, system->getMasterName(i)); 1789 } 1790 1791 overallAvgMissLatency 1792 .name(name() + ".overall_avg_miss_latency") 1793 .desc("average overall miss latency") 1794 .flags(total | nozero | nonan) 1795 ; 1796 overallAvgMissLatency = overallMissLatency / overallMisses; 1797 for (int i = 0; i < system->maxMasters(); i++) { 1798 overallAvgMissLatency.subname(i, system->getMasterName(i)); 1799 } 1800 1801 blocked_cycles.init(NUM_BLOCKED_CAUSES); 1802 blocked_cycles 1803 .name(name() + ".blocked_cycles") 1804 .desc("number of cycles access was blocked") 1805 .subname(Blocked_NoMSHRs, "no_mshrs") 1806 .subname(Blocked_NoTargets, "no_targets") 1807 ; 1808 1809 1810 blocked_causes.init(NUM_BLOCKED_CAUSES); 1811 blocked_causes 1812 .name(name() + ".blocked") 1813 .desc("number of cycles access was blocked") 1814 .subname(Blocked_NoMSHRs, "no_mshrs") 1815 .subname(Blocked_NoTargets, "no_targets") 1816 ; 1817 1818 avg_blocked 1819 .name(name() + ".avg_blocked_cycles") 1820 .desc("average number of cycles each access was blocked") 1821 .subname(Blocked_NoMSHRs, "no_mshrs") 1822 .subname(Blocked_NoTargets, "no_targets") 1823 ; 1824 1825 avg_blocked = blocked_cycles / blocked_causes; 1826 1827 unusedPrefetches 1828 .name(name() + ".unused_prefetches") 1829 .desc("number of HardPF blocks evicted w/o reference") 1830 .flags(nozero) 1831 ; 1832 1833 writebacks 1834 .init(system->maxMasters()) 1835 .name(name() + ".writebacks") 1836 .desc("number of writebacks") 1837 .flags(total | nozero | nonan) 1838 ; 1839 for (int i = 0; i < system->maxMasters(); i++) { 1840 writebacks.subname(i, system->getMasterName(i)); 1841 } 1842 1843 // MSHR statistics 1844 // MSHR hit statistics 1845 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1846 MemCmd cmd(access_idx); 1847 const string &cstr = cmd.toString(); 1848 1849 mshr_hits[access_idx] 1850 .init(system->maxMasters()) 1851 .name(name() + "." + cstr + "_mshr_hits") 1852 .desc("number of " + cstr + " MSHR hits") 1853 .flags(total | nozero | nonan) 1854 ; 1855 for (int i = 0; i < system->maxMasters(); i++) { 1856 mshr_hits[access_idx].subname(i, system->getMasterName(i)); 1857 } 1858 } 1859 1860 demandMshrHits 1861 .name(name() + ".demand_mshr_hits") 1862 .desc("number of demand (read+write) MSHR hits") 1863 .flags(total | nozero | nonan) 1864 ; 1865 demandMshrHits = SUM_DEMAND(mshr_hits); 1866 for (int i = 0; i < system->maxMasters(); i++) { 1867 demandMshrHits.subname(i, system->getMasterName(i)); 1868 } 1869 1870 overallMshrHits 1871 .name(name() + ".overall_mshr_hits") 1872 .desc("number of overall MSHR hits") 1873 .flags(total | nozero | nonan) 1874 ; 1875 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 1876 for (int i = 0; i < system->maxMasters(); i++) { 1877 overallMshrHits.subname(i, system->getMasterName(i)); 1878 } 1879 1880 // MSHR miss statistics 1881 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1882 MemCmd cmd(access_idx); 1883 const string &cstr = cmd.toString(); 1884 1885 mshr_misses[access_idx] 1886 .init(system->maxMasters()) 1887 .name(name() + "." + cstr + "_mshr_misses") 1888 .desc("number of " + cstr + " MSHR misses") 1889 .flags(total | nozero | nonan) 1890 ; 1891 for (int i = 0; i < system->maxMasters(); i++) { 1892 mshr_misses[access_idx].subname(i, system->getMasterName(i)); 1893 } 1894 } 1895 1896 demandMshrMisses 1897 .name(name() + ".demand_mshr_misses") 1898 .desc("number of demand (read+write) MSHR misses") 1899 .flags(total | nozero | nonan) 1900 ; 1901 demandMshrMisses = SUM_DEMAND(mshr_misses); 1902 for (int i = 0; i < system->maxMasters(); i++) { 1903 demandMshrMisses.subname(i, system->getMasterName(i)); 1904 } 1905 1906 overallMshrMisses 1907 .name(name() + ".overall_mshr_misses") 1908 .desc("number of overall MSHR misses") 1909 .flags(total | nozero | nonan) 1910 ; 1911 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 1912 for (int i = 0; i < system->maxMasters(); i++) { 1913 overallMshrMisses.subname(i, system->getMasterName(i)); 1914 } 1915 1916 // MSHR miss latency statistics 1917 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1918 MemCmd cmd(access_idx); 1919 const string &cstr = cmd.toString(); 1920 1921 mshr_miss_latency[access_idx] 1922 .init(system->maxMasters()) 1923 .name(name() + "." + cstr + "_mshr_miss_latency") 1924 .desc("number of " + cstr + " MSHR miss cycles") 1925 .flags(total | nozero | nonan) 1926 ; 1927 for (int i = 0; i < system->maxMasters(); i++) { 1928 mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 1929 } 1930 } 1931 1932 demandMshrMissLatency 1933 .name(name() + ".demand_mshr_miss_latency") 1934 .desc("number of demand (read+write) MSHR miss cycles") 1935 .flags(total | nozero | nonan) 1936 ; 1937 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 1938 for (int i = 0; i < system->maxMasters(); i++) { 1939 demandMshrMissLatency.subname(i, system->getMasterName(i)); 1940 } 1941 1942 overallMshrMissLatency 1943 .name(name() + ".overall_mshr_miss_latency") 1944 .desc("number of overall MSHR miss cycles") 1945 .flags(total | nozero | nonan) 1946 ; 1947 overallMshrMissLatency = 1948 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 1949 for (int i = 0; i < system->maxMasters(); i++) { 1950 overallMshrMissLatency.subname(i, system->getMasterName(i)); 1951 } 1952 1953 // MSHR uncacheable statistics 1954 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1955 MemCmd cmd(access_idx); 1956 const string &cstr = cmd.toString(); 1957 1958 mshr_uncacheable[access_idx] 1959 .init(system->maxMasters()) 1960 .name(name() + "." + cstr + "_mshr_uncacheable") 1961 .desc("number of " + cstr + " MSHR uncacheable") 1962 .flags(total | nozero | nonan) 1963 ; 1964 for (int i = 0; i < system->maxMasters(); i++) { 1965 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 1966 } 1967 } 1968 1969 overallMshrUncacheable 1970 .name(name() + ".overall_mshr_uncacheable_misses") 1971 .desc("number of overall MSHR uncacheable misses") 1972 .flags(total | nozero | nonan) 1973 ; 1974 overallMshrUncacheable = 1975 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 1976 for (int i = 0; i < system->maxMasters(); i++) { 1977 overallMshrUncacheable.subname(i, system->getMasterName(i)); 1978 } 1979 1980 // MSHR miss latency statistics 1981 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1982 MemCmd cmd(access_idx); 1983 const string &cstr = cmd.toString(); 1984 1985 mshr_uncacheable_lat[access_idx] 1986 .init(system->maxMasters()) 1987 .name(name() + "." + cstr + "_mshr_uncacheable_latency") 1988 .desc("number of " + cstr + " MSHR uncacheable cycles") 1989 .flags(total | nozero | nonan) 1990 ; 1991 for (int i = 0; i < system->maxMasters(); i++) { 1992 mshr_uncacheable_lat[access_idx].subname( 1993 i, system->getMasterName(i)); 1994 } 1995 } 1996 1997 overallMshrUncacheableLatency 1998 .name(name() + ".overall_mshr_uncacheable_latency") 1999 .desc("number of overall MSHR uncacheable cycles") 2000 .flags(total | nozero | nonan) 2001 ; 2002 overallMshrUncacheableLatency = 2003 SUM_DEMAND(mshr_uncacheable_lat) + 2004 SUM_NON_DEMAND(mshr_uncacheable_lat); 2005 for (int i = 0; i < system->maxMasters(); i++) { 2006 overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 2007 } 2008 2009#if 0 2010 // MSHR access formulas 2011 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2012 MemCmd cmd(access_idx); 2013 const string &cstr = cmd.toString(); 2014 2015 mshrAccesses[access_idx] 2016 .name(name() + "." + cstr + "_mshr_accesses") 2017 .desc("number of " + cstr + " mshr accesses(hits+misses)") 2018 .flags(total | nozero | nonan) 2019 ; 2020 mshrAccesses[access_idx] = 2021 mshr_hits[access_idx] + mshr_misses[access_idx] 2022 + mshr_uncacheable[access_idx]; 2023 } 2024 2025 demandMshrAccesses 2026 .name(name() + ".demand_mshr_accesses") 2027 .desc("number of demand (read+write) mshr accesses") 2028 .flags(total | nozero | nonan) 2029 ; 2030 demandMshrAccesses = demandMshrHits + demandMshrMisses; 2031 2032 overallMshrAccesses 2033 .name(name() + ".overall_mshr_accesses") 2034 .desc("number of overall (read+write) mshr accesses") 2035 .flags(total | nozero | nonan) 2036 ; 2037 overallMshrAccesses = overallMshrHits + overallMshrMisses 2038 + overallMshrUncacheable; 2039#endif 2040 2041 // MSHR miss rate formulas 2042 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2043 MemCmd cmd(access_idx); 2044 const string &cstr = cmd.toString(); 2045 2046 mshrMissRate[access_idx] 2047 .name(name() + "." + cstr + "_mshr_miss_rate") 2048 .desc("mshr miss rate for " + cstr + " accesses") 2049 .flags(total | nozero | nonan) 2050 ; 2051 mshrMissRate[access_idx] = 2052 mshr_misses[access_idx] / accesses[access_idx]; 2053 2054 for (int i = 0; i < system->maxMasters(); i++) { 2055 mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 2056 } 2057 } 2058 2059 demandMshrMissRate 2060 .name(name() + ".demand_mshr_miss_rate") 2061 .desc("mshr miss rate for demand accesses") 2062 .flags(total | nozero | nonan) 2063 ; 2064 demandMshrMissRate = demandMshrMisses / demandAccesses; 2065 for (int i = 0; i < system->maxMasters(); i++) { 2066 demandMshrMissRate.subname(i, system->getMasterName(i)); 2067 } 2068 2069 overallMshrMissRate 2070 .name(name() + ".overall_mshr_miss_rate") 2071 .desc("mshr miss rate for overall accesses") 2072 .flags(total | nozero | nonan) 2073 ; 2074 overallMshrMissRate = overallMshrMisses / overallAccesses; 2075 for (int i = 0; i < system->maxMasters(); i++) { 2076 overallMshrMissRate.subname(i, system->getMasterName(i)); 2077 } 2078 2079 // mshrMiss latency formulas 2080 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2081 MemCmd cmd(access_idx); 2082 const string &cstr = cmd.toString(); 2083 2084 avgMshrMissLatency[access_idx] 2085 .name(name() + "." + cstr + "_avg_mshr_miss_latency") 2086 .desc("average " + cstr + " mshr miss latency") 2087 .flags(total | nozero | nonan) 2088 ; 2089 avgMshrMissLatency[access_idx] = 2090 mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 2091 2092 for (int i = 0; i < system->maxMasters(); i++) { 2093 avgMshrMissLatency[access_idx].subname( 2094 i, system->getMasterName(i)); 2095 } 2096 } 2097 2098 demandAvgMshrMissLatency 2099 .name(name() + ".demand_avg_mshr_miss_latency") 2100 .desc("average overall mshr miss latency") 2101 .flags(total | nozero | nonan) 2102 ; 2103 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 2104 for (int i = 0; i < system->maxMasters(); i++) { 2105 demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 2106 } 2107 2108 overallAvgMshrMissLatency 2109 .name(name() + ".overall_avg_mshr_miss_latency") 2110 .desc("average overall mshr miss latency") 2111 .flags(total | nozero | nonan) 2112 ; 2113 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 2114 for (int i = 0; i < system->maxMasters(); i++) { 2115 overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 2116 } 2117 2118 // mshrUncacheable latency formulas 2119 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2120 MemCmd cmd(access_idx); 2121 const string &cstr = cmd.toString(); 2122 2123 avgMshrUncacheableLatency[access_idx] 2124 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 2125 .desc("average " + cstr + " mshr uncacheable latency") 2126 .flags(total | nozero | nonan) 2127 ; 2128 avgMshrUncacheableLatency[access_idx] = 2129 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 2130 2131 for (int i = 0; i < system->maxMasters(); i++) { 2132 avgMshrUncacheableLatency[access_idx].subname( 2133 i, system->getMasterName(i)); 2134 } 2135 } 2136 2137 overallAvgMshrUncacheableLatency 2138 .name(name() + ".overall_avg_mshr_uncacheable_latency") 2139 .desc("average overall mshr uncacheable latency") 2140 .flags(total | nozero | nonan) 2141 ; 2142 overallAvgMshrUncacheableLatency = 2143 overallMshrUncacheableLatency / overallMshrUncacheable; 2144 for (int i = 0; i < system->maxMasters(); i++) { 2145 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 2146 } 2147 2148 replacements 2149 .name(name() + ".replacements") 2150 .desc("number of replacements") 2151 ; 2152} 2153 2154/////////////// 2155// 2156// CpuSidePort 2157// 2158/////////////// 2159bool 2160BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 2161{ 2162 // Snoops shouldn't happen when bypassing caches 2163 assert(!cache->system->bypassCaches()); 2164 2165 assert(pkt->isResponse()); 2166 2167 // Express snoop responses from master to slave, e.g., from L1 to L2 2168 cache->recvTimingSnoopResp(pkt); 2169 return true; 2170} 2171 2172 2173bool 2174BaseCache::CpuSidePort::tryTiming(PacketPtr pkt) 2175{ 2176 if (cache->system->bypassCaches() || pkt->isExpressSnoop()) { 2177 // always let express snoop packets through even if blocked 2178 return true; 2179 } else if (blocked || mustSendRetry) { 2180 // either already committed to send a retry, or blocked 2181 mustSendRetry = true; 2182 return false; 2183 } 2184 mustSendRetry = false; 2185 return true; 2186} 2187 2188bool 2189BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 2190{ 2191 assert(pkt->isRequest()); 2192 2193 if (cache->system->bypassCaches()) { 2194 // Just forward the packet if caches are disabled. 2195 // @todo This should really enqueue the packet rather 2196 bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt); 2197 assert(success); 2198 return true; 2199 } else if (tryTiming(pkt)) { 2200 cache->recvTimingReq(pkt); 2201 return true; 2202 } 2203 return false; 2204} 2205 2206Tick 2207BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt) 2208{ 2209 if (cache->system->bypassCaches()) { 2210 // Forward the request if the system is in cache bypass mode. 2211 return cache->memSidePort.sendAtomic(pkt); 2212 } else { 2213 return cache->recvAtomic(pkt); 2214 } 2215} 2216 2217void 2218BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt) 2219{ 2220 if (cache->system->bypassCaches()) { 2221 // The cache should be flushed if we are in cache bypass mode, 2222 // so we don't need to check if we need to update anything. 2223 cache->memSidePort.sendFunctional(pkt); 2224 return; 2225 } 2226 2227 // functional request 2228 cache->functionalAccess(pkt, true); 2229} 2230 2231AddrRangeList 2232BaseCache::CpuSidePort::getAddrRanges() const 2233{ 2234 return cache->getAddrRanges(); 2235} 2236 2237 2238BaseCache:: 2239CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache, 2240 const std::string &_label) 2241 : CacheSlavePort(_name, _cache, _label), cache(_cache) 2242{ 2243} 2244 2245/////////////// 2246// 2247// MemSidePort 2248// 2249/////////////// 2250bool 2251BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 2252{ 2253 cache->recvTimingResp(pkt); 2254 return true; 2255} 2256 2257// Express snooping requests to memside port 2258void 2259BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 2260{ 2261 // Snoops shouldn't happen when bypassing caches 2262 assert(!cache->system->bypassCaches()); 2263 2264 // handle snooping requests 2265 cache->recvTimingSnoopReq(pkt); 2266} 2267 2268Tick 2269BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 2270{ 2271 // Snoops shouldn't happen when bypassing caches 2272 assert(!cache->system->bypassCaches()); 2273 2274 return cache->recvAtomicSnoop(pkt); 2275} 2276 2277void 2278BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 2279{ 2280 // Snoops shouldn't happen when bypassing caches 2281 assert(!cache->system->bypassCaches()); 2282 2283 // functional snoop (note that in contrast to atomic we don't have 2284 // a specific functionalSnoop method, as they have the same 2285 // behaviour regardless) 2286 cache->functionalAccess(pkt, false); 2287} 2288 2289void 2290BaseCache::CacheReqPacketQueue::sendDeferredPacket() 2291{ 2292 // sanity check 2293 assert(!waitingOnRetry); 2294 2295 // there should never be any deferred request packets in the 2296 // queue, instead we resly on the cache to provide the packets 2297 // from the MSHR queue or write queue 2298 assert(deferredPacketReadyTime() == MaxTick); 2299 2300 // check for request packets (requests & writebacks) 2301 QueueEntry* entry = cache.getNextQueueEntry(); 2302 2303 if (!entry) { 2304 // can happen if e.g. we attempt a writeback and fail, but 2305 // before the retry, the writeback is eliminated because 2306 // we snoop another cache's ReadEx. 2307 } else { 2308 // let our snoop responses go first if there are responses to 2309 // the same addresses 2310 if (checkConflictingSnoop(entry->blkAddr)) { 2311 return; 2312 } 2313 waitingOnRetry = entry->sendPacket(cache); 2314 } 2315 2316 // if we succeeded and are not waiting for a retry, schedule the 2317 // next send considering when the next queue is ready, note that 2318 // snoop responses have their own packet queue and thus schedule 2319 // their own events 2320 if (!waitingOnRetry) { 2321 schedSendEvent(cache.nextQueueReadyTime()); 2322 } 2323} 2324 2325BaseCache::MemSidePort::MemSidePort(const std::string &_name, 2326 BaseCache *_cache, 2327 const std::string &_label) 2328 : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 2329 _reqQueue(*_cache, *this, _snoopRespQueue, _label), 2330 _snoopRespQueue(*_cache, *this, _label), cache(_cache) 2331{ 2332}
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