1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Nikos Nikoleris
42 */
43
44/**
45 * @file
46 * Definition of BaseCache functions.
47 */
48
49#include "mem/cache/base.hh"
50
51#include "base/compiler.hh"
52#include "base/logging.hh"
53#include "debug/Cache.hh"
54#include "debug/CachePort.hh"
55#include "debug/CacheVerbose.hh"
56#include "mem/cache/mshr.hh"
57#include "mem/cache/prefetch/base.hh"
58#include "mem/cache/queue_entry.hh"
59#include "params/BaseCache.hh"
60#include "sim/core.hh"
61
62class BaseMasterPort;
63class BaseSlavePort;
64
65using namespace std;
66
67BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
68 BaseCache *_cache,
69 const std::string &_label)
70 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
71 blocked(false), mustSendRetry(false),
72 sendRetryEvent([this]{ processSendRetry(); }, _name)
73{
74}
75
76BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
77 : MemObject(p),
78 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
79 memSidePort(p->name + ".mem_side", this, "MemSidePort"),
80 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
81 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
82 tags(p->tags),
83 prefetcher(p->prefetcher),
84 prefetchOnAccess(p->prefetch_on_access),
85 writebackClean(p->writeback_clean),
86 tempBlockWriteback(nullptr),
87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
88 name(), false,
89 EventBase::Delayed_Writeback_Pri),
90 blkSize(blk_size),
91 lookupLatency(p->tag_latency),
92 dataLatency(p->data_latency),
93 forwardLatency(p->tag_latency),
94 fillLatency(p->data_latency),
95 responseLatency(p->response_latency),
96 numTarget(p->tgts_per_mshr),
97 forwardSnoops(true),
98 clusivity(p->clusivity),
99 isReadOnly(p->is_read_only),
100 blocked(0),
101 order(0),
102 noTargetMSHR(nullptr),
103 missCount(p->max_miss_count),
104 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
105 system(p->system)
106{
107 // the MSHR queue has no reserve entries as we check the MSHR
108 // queue on every single allocation, whereas the write queue has
109 // as many reserve entries as we have MSHRs, since every MSHR may
110 // eventually require a writeback, and we do not check the write
111 // buffer before committing to an MSHR
112
113 // forward snoops is overridden in init() once we can query
114 // whether the connected master is actually snooping or not
115
116 tempBlock = new TempCacheBlk();
117 tempBlock->data = new uint8_t[blkSize];
118
119 tags->setCache(this);
120 if (prefetcher)
121 prefetcher->setCache(this);
122}
123
124BaseCache::~BaseCache()
125{
126 delete [] tempBlock->data;
127 delete tempBlock;
128}
129
130void
131BaseCache::CacheSlavePort::setBlocked()
132{
133 assert(!blocked);
134 DPRINTF(CachePort, "Port is blocking new requests\n");
135 blocked = true;
136 // if we already scheduled a retry in this cycle, but it has not yet
137 // happened, cancel it
138 if (sendRetryEvent.scheduled()) {
139 owner.deschedule(sendRetryEvent);
140 DPRINTF(CachePort, "Port descheduled retry\n");
141 mustSendRetry = true;
142 }
143}
144
145void
146BaseCache::CacheSlavePort::clearBlocked()
147{
148 assert(blocked);
149 DPRINTF(CachePort, "Port is accepting new requests\n");
150 blocked = false;
151 if (mustSendRetry) {
152 // @TODO: need to find a better time (next cycle?)
153 owner.schedule(sendRetryEvent, curTick() + 1);
154 }
155}
156
157void
158BaseCache::CacheSlavePort::processSendRetry()
159{
160 DPRINTF(CachePort, "Port is sending retry\n");
161
162 // reset the flag and call retry
163 mustSendRetry = false;
164 sendRetryReq();
165}
166
167Addr
168BaseCache::regenerateBlkAddr(CacheBlk* blk)
169{
170 if (blk != tempBlock) {
171 return tags->regenerateBlkAddr(blk);
172 } else {
173 return tempBlock->getAddr();
174 }
175}
176
177void
178BaseCache::init()
179{
180 if (!cpuSidePort.isConnected() || !memSidePort.isConnected())
181 fatal("Cache ports on %s are not connected\n", name());
182 cpuSidePort.sendRangeChange();
183 forwardSnoops = cpuSidePort.isSnooping();
184}
185
186BaseMasterPort &
187BaseCache::getMasterPort(const std::string &if_name, PortID idx)
188{
189 if (if_name == "mem_side") {
190 return memSidePort;
191 } else {
192 return MemObject::getMasterPort(if_name, idx);
193 }
194}
195
196BaseSlavePort &
197BaseCache::getSlavePort(const std::string &if_name, PortID idx)
198{
199 if (if_name == "cpu_side") {
200 return cpuSidePort;
201 } else {
202 return MemObject::getSlavePort(if_name, idx);
203 }
204}
205
206bool
207BaseCache::inRange(Addr addr) const
208{
209 for (const auto& r : addrRanges) {
210 if (r.contains(addr)) {
211 return true;
212 }
213 }
214 return false;
215}
216
217void
218BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
219{
220 if (pkt->needsResponse()) {
221 pkt->makeTimingResponse();
222 // @todo: Make someone pay for this
223 pkt->headerDelay = pkt->payloadDelay = 0;
224
225 // In this case we are considering request_time that takes
226 // into account the delay of the xbar, if any, and just
227 // lat, neglecting responseLatency, modelling hit latency
228 // just as lookupLatency or or the value of lat overriden
229 // by access(), that calls accessBlock() function.
230 cpuSidePort.schedTimingResp(pkt, request_time, true);
231 } else {
232 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
233 pkt->print());
234
235 // queue the packet for deletion, as the sending cache is
236 // still relying on it; if the block is found in access(),
237 // CleanEvict and Writeback messages will be deleted
238 // here as well
239 pendingDelete.reset(pkt);
240 }
241}
242
243void
244BaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
245 Tick forward_time, Tick request_time)
246{
247 if (mshr) {
248 /// MSHR hit
249 /// @note writebacks will be checked in getNextMSHR()
250 /// for any conflicting requests to the same block
251
252 //@todo remove hw_pf here
253
254 // Coalesce unless it was a software prefetch (see above).
255 if (pkt) {
256 assert(!pkt->isWriteback());
257 // CleanEvicts corresponding to blocks which have
258 // outstanding requests in MSHRs are simply sunk here
259 if (pkt->cmd == MemCmd::CleanEvict) {
260 pendingDelete.reset(pkt);
261 } else if (pkt->cmd == MemCmd::WriteClean) {
262 // A WriteClean should never coalesce with any
263 // outstanding cache maintenance requests.
264
265 // We use forward_time here because there is an
266 // uncached memory write, forwarded to WriteBuffer.
267 allocateWriteBuffer(pkt, forward_time);
268 } else {
269 DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__,
270 pkt->print());
271
272 assert(pkt->req->masterId() < system->maxMasters());
273 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
274
275 // We use forward_time here because it is the same
276 // considering new targets. We have multiple
277 // requests for the same address here. It
278 // specifies the latency to allocate an internal
279 // buffer and to schedule an event to the queued
280 // port and also takes into account the additional
281 // delay of the xbar.
282 mshr->allocateTarget(pkt, forward_time, order++,
283 allocOnFill(pkt->cmd));
284 if (mshr->getNumTargets() == numTarget) {
285 noTargetMSHR = mshr;
286 setBlocked(Blocked_NoTargets);
287 // need to be careful with this... if this mshr isn't
288 // ready yet (i.e. time > curTick()), we don't want to
289 // move it ahead of mshrs that are ready
290 // mshrQueue.moveToFront(mshr);
291 }
292 }
293 }
294 } else {
295 // no MSHR
296 assert(pkt->req->masterId() < system->maxMasters());
297 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
298
299 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) {
300 // We use forward_time here because there is an
301 // writeback or writeclean, forwarded to WriteBuffer.
302 allocateWriteBuffer(pkt, forward_time);
303 } else {
304 if (blk && blk->isValid()) {
305 // If we have a write miss to a valid block, we
306 // need to mark the block non-readable. Otherwise
307 // if we allow reads while there's an outstanding
308 // write miss, the read could return stale data
309 // out of the cache block... a more aggressive
310 // system could detect the overlap (if any) and
311 // forward data out of the MSHRs, but we don't do
312 // that yet. Note that we do need to leave the
313 // block valid so that it stays in the cache, in
314 // case we get an upgrade response (and hence no
315 // new data) when the write miss completes.
316 // As long as CPUs do proper store/load forwarding
317 // internally, and have a sufficiently weak memory
318 // model, this is probably unnecessary, but at some
319 // point it must have seemed like we needed it...
320 assert((pkt->needsWritable() && !blk->isWritable()) ||
321 pkt->req->isCacheMaintenance());
322 blk->status &= ~BlkReadable;
323 }
324 // Here we are using forward_time, modelling the latency of
325 // a miss (outbound) just as forwardLatency, neglecting the
326 // lookupLatency component.
327 allocateMissBuffer(pkt, forward_time);
328 }
329 }
330}
331
332void
333BaseCache::recvTimingReq(PacketPtr pkt)
334{
335 // anything that is merely forwarded pays for the forward latency and
336 // the delay provided by the crossbar
337 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
338
339 // We use lookupLatency here because it is used to specify the latency
340 // to access.
341 Cycles lat = lookupLatency;
342 CacheBlk *blk = nullptr;
343 bool satisfied = false;
344 {
345 PacketList writebacks;
346 // Note that lat is passed by reference here. The function
347 // access() calls accessBlock() which can modify lat value.
348 satisfied = access(pkt, blk, lat, writebacks);
349
350 // copy writebacks to write buffer here to ensure they logically
351 // proceed anything happening below
352 doWritebacks(writebacks, forward_time);
353 }
354
355 // Here we charge the headerDelay that takes into account the latencies
356 // of the bus, if the packet comes from it.
357 // The latency charged it is just lat that is the value of lookupLatency
358 // modified by access() function, or if not just lookupLatency.
359 // In case of a hit we are neglecting response latency.
360 // In case of a miss we are neglecting forward latency.
361 Tick request_time = clockEdge(lat) + pkt->headerDelay;
362 // Here we reset the timing of the packet.
363 pkt->headerDelay = pkt->payloadDelay = 0;
364 // track time of availability of next prefetch, if any
365 Tick next_pf_time = MaxTick;
366
367 if (satisfied) {
368 // if need to notify the prefetcher we have to do it before
369 // anything else as later handleTimingReqHit might turn the
370 // packet in a response
371 if (prefetcher &&
372 (prefetchOnAccess || (blk && blk->wasPrefetched()))) {
373 if (blk)
374 blk->status &= ~BlkHWPrefetched;
375
376 // Don't notify on SWPrefetch
377 if (!pkt->cmd.isSWPrefetch()) {
378 assert(!pkt->req->isCacheMaintenance());
379 next_pf_time = prefetcher->notify(pkt);
380 }
381 }
382
383 handleTimingReqHit(pkt, blk, request_time);
384 } else {
385 handleTimingReqMiss(pkt, blk, forward_time, request_time);
386
387 // We should call the prefetcher reguardless if the request is
388 // satisfied or not, reguardless if the request is in the MSHR
389 // or not. The request could be a ReadReq hit, but still not
390 // satisfied (potentially because of a prior write to the same
391 // cache line. So, even when not satisfied, there is an MSHR
392 // already allocated for this, we need to let the prefetcher
393 // know about the request
394
395 // Don't notify prefetcher on SWPrefetch or cache maintenance
396 // operations
397 if (prefetcher && pkt &&
398 !pkt->cmd.isSWPrefetch() &&
399 !pkt->req->isCacheMaintenance()) {
400 next_pf_time = prefetcher->notify(pkt);
401 }
402 }
403
404 if (next_pf_time != MaxTick) {
405 schedMemSideSendEvent(next_pf_time);
406 }
407}
408
409void
410BaseCache::handleUncacheableWriteResp(PacketPtr pkt)
411{
412 Tick completion_time = clockEdge(responseLatency) +
413 pkt->headerDelay + pkt->payloadDelay;
414
415 // Reset the bus additional time as it is now accounted for
416 pkt->headerDelay = pkt->payloadDelay = 0;
417
418 cpuSidePort.schedTimingResp(pkt, completion_time, true);
419}
420
421void
422BaseCache::recvTimingResp(PacketPtr pkt)
423{
424 assert(pkt->isResponse());
425
426 // all header delay should be paid for by the crossbar, unless
427 // this is a prefetch response from above
428 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
429 "%s saw a non-zero packet delay\n", name());
430
431 const bool is_error = pkt->isError();
432
433 if (is_error) {
434 DPRINTF(Cache, "%s: Cache received %s with error\n", __func__,
435 pkt->print());
436 }
437
438 DPRINTF(Cache, "%s: Handling response %s\n", __func__,
439 pkt->print());
440
441 // if this is a write, we should be looking at an uncacheable
442 // write
443 if (pkt->isWrite()) {
444 assert(pkt->req->isUncacheable());
445 handleUncacheableWriteResp(pkt);
446 return;
447 }
448
449 // we have dealt with any (uncacheable) writes above, from here on
450 // we know we are dealing with an MSHR due to a miss or a prefetch
451 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
452 assert(mshr);
453
454 if (mshr == noTargetMSHR) {
455 // we always clear at least one target
456 clearBlocked(Blocked_NoTargets);
457 noTargetMSHR = nullptr;
458 }
459
460 // Initial target is used just for stats
461 MSHR::Target *initial_tgt = mshr->getTarget();
462 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
463 Tick miss_latency = curTick() - initial_tgt->recvTime;
464
465 if (pkt->req->isUncacheable()) {
466 assert(pkt->req->masterId() < system->maxMasters());
467 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
468 miss_latency;
469 } else {
470 assert(pkt->req->masterId() < system->maxMasters());
471 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
472 miss_latency;
473 }
474
475 PacketList writebacks;
476
477 bool is_fill = !mshr->isForward &&
478 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
479
480 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
481
482 if (is_fill && !is_error) {
483 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
484 pkt->getAddr());
485
486 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill());
487 assert(blk != nullptr);
488 }
489
490 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) {
491 // The block was marked not readable while there was a pending
492 // cache maintenance operation, restore its flag.
493 blk->status |= BlkReadable;
494 }
495
496 if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) {
497 // If at this point the referenced block is writable and the
498 // response is not a cache invalidate, we promote targets that
499 // were deferred as we couldn't guarrantee a writable copy
500 mshr->promoteWritable();
501 }
502
503 serviceMSHRTargets(mshr, pkt, blk, writebacks);
504
505 if (mshr->promoteDeferredTargets()) {
506 // avoid later read getting stale data while write miss is
507 // outstanding.. see comment in timingAccess()
508 if (blk) {
509 blk->status &= ~BlkReadable;
510 }
511 mshrQueue.markPending(mshr);
512 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
513 } else {
514 // while we deallocate an mshr from the queue we still have to
515 // check the isFull condition before and after as we might
516 // have been using the reserved entries already
517 const bool was_full = mshrQueue.isFull();
518 mshrQueue.deallocate(mshr);
519 if (was_full && !mshrQueue.isFull()) {
520 clearBlocked(Blocked_NoMSHRs);
521 }
522
523 // Request the bus for a prefetch if this deallocation freed enough
524 // MSHRs for a prefetch to take place
525 if (prefetcher && mshrQueue.canPrefetch()) {
526 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
527 clockEdge());
528 if (next_pf_time != MaxTick)
529 schedMemSideSendEvent(next_pf_time);
530 }
531 }
532
533 // if we used temp block, check to see if its valid and then clear it out
534 if (blk == tempBlock && tempBlock->isValid()) {
535 evictBlock(blk, writebacks);
536 }
537
538 const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
539 // copy writebacks to write buffer
540 doWritebacks(writebacks, forward_time);
541
542 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
543 delete pkt;
544}
545
546
547Tick
548BaseCache::recvAtomic(PacketPtr pkt)
549{
550 // We are in atomic mode so we pay just for lookupLatency here.
551 Cycles lat = lookupLatency;
552
553 // follow the same flow as in recvTimingReq, and check if a cache
554 // above us is responding
555 if (pkt->cacheResponding() && !pkt->isClean()) {
556 assert(!pkt->req->isCacheInvalidate());
557 DPRINTF(Cache, "Cache above responding to %s: not responding\n",
558 pkt->print());
559
560 // if a cache is responding, and it had the line in Owned
561 // rather than Modified state, we need to invalidate any
562 // copies that are not on the same path to memory
563 assert(pkt->needsWritable() && !pkt->responderHadWritable());
564 lat += ticksToCycles(memSidePort.sendAtomic(pkt));
565
566 return lat * clockPeriod();
567 }
568
569 // should assert here that there are no outstanding MSHRs or
570 // writebacks... that would mean that someone used an atomic
571 // access in timing mode
572
573 CacheBlk *blk = nullptr;
574 PacketList writebacks;
575 bool satisfied = access(pkt, blk, lat, writebacks);
576
577 if (pkt->isClean() && blk && blk->isDirty()) {
578 // A cache clean opearation is looking for a dirty
579 // block. If a dirty block is encountered a WriteClean
580 // will update any copies to the path to the memory
581 // until the point of reference.
582 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
583 __func__, pkt->print(), blk->print());
584 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
585 writebacks.push_back(wb_pkt);
586 pkt->setSatisfied();
587 }
588
589 // handle writebacks resulting from the access here to ensure they
590 // logically proceed anything happening below
591 doWritebacksAtomic(writebacks);
592 assert(writebacks.empty());
593
594 if (!satisfied) {
595 lat += handleAtomicReqMiss(pkt, blk, writebacks);
596 }
597
598 // Note that we don't invoke the prefetcher at all in atomic mode.
599 // It's not clear how to do it properly, particularly for
600 // prefetchers that aggressively generate prefetch candidates and
601 // rely on bandwidth contention to throttle them; these will tend
602 // to pollute the cache in atomic mode since there is no bandwidth
603 // contention. If we ever do want to enable prefetching in atomic
604 // mode, though, this is the place to do it... see timingAccess()
605 // for an example (though we'd want to issue the prefetch(es)
606 // immediately rather than calling requestMemSideBus() as we do
607 // there).
608
609 // do any writebacks resulting from the response handling
610 doWritebacksAtomic(writebacks);
611
612 // if we used temp block, check to see if its valid and if so
613 // clear it out, but only do so after the call to recvAtomic is
614 // finished so that any downstream observers (such as a snoop
615 // filter), first see the fill, and only then see the eviction
616 if (blk == tempBlock && tempBlock->isValid()) {
617 // the atomic CPU calls recvAtomic for fetch and load/store
618 // sequentuially, and we may already have a tempBlock
619 // writeback from the fetch that we have not yet sent
620 if (tempBlockWriteback) {
621 // if that is the case, write the prevoius one back, and
622 // do not schedule any new event
623 writebackTempBlockAtomic();
624 } else {
625 // the writeback/clean eviction happens after the call to
626 // recvAtomic has finished (but before any successive
627 // calls), so that the response handling from the fill is
628 // allowed to happen first
629 schedule(writebackTempBlockAtomicEvent, curTick());
630 }
631
632 tempBlockWriteback = evictBlock(blk);
633 }
634
635 if (pkt->needsResponse()) {
636 pkt->makeAtomicResponse();
637 }
638
639 return lat * clockPeriod();
640}
641
642void
643BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
644{
645 Addr blk_addr = pkt->getBlockAddr(blkSize);
646 bool is_secure = pkt->isSecure();
647 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
648 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
649
650 pkt->pushLabel(name());
651
652 CacheBlkPrintWrapper cbpw(blk);
653
654 // Note that just because an L2/L3 has valid data doesn't mean an
655 // L1 doesn't have a more up-to-date modified copy that still
656 // needs to be found. As a result we always update the request if
657 // we have it, but only declare it satisfied if we are the owner.
658
659 // see if we have data at all (owned or otherwise)
660 bool have_data = blk && blk->isValid()
661 && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
662 blk->data);
663
664 // data we have is dirty if marked as such or if we have an
665 // in-service MSHR that is pending a modified line
666 bool have_dirty =
667 have_data && (blk->isDirty() ||
668 (mshr && mshr->inService && mshr->isPendingModified()));
669
670 bool done = have_dirty ||
671 cpuSidePort.checkFunctional(pkt) ||
672 mshrQueue.checkFunctional(pkt, blk_addr) ||
673 writeBuffer.checkFunctional(pkt, blk_addr) ||
674 memSidePort.checkFunctional(pkt);
675
676 DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(),
677 (blk && blk->isValid()) ? "valid " : "",
678 have_data ? "data " : "", done ? "done " : "");
679
680 // We're leaving the cache, so pop cache->name() label
681 pkt->popLabel();
682
683 if (done) {
684 pkt->makeResponse();
685 } else {
686 // if it came as a request from the CPU side then make sure it
687 // continues towards the memory side
688 if (from_cpu_side) {
689 memSidePort.sendFunctional(pkt);
690 } else if (cpuSidePort.isSnooping()) {
691 // if it came from the memory side, it must be a snoop request
692 // and we should only forward it if we are forwarding snoops
693 cpuSidePort.sendFunctionalSnoop(pkt);
694 }
695 }
696}
697
698
699void
700BaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
701{
702 assert(pkt->isRequest());
703
704 uint64_t overwrite_val;
705 bool overwrite_mem;
706 uint64_t condition_val64;
707 uint32_t condition_val32;
708
709 int offset = pkt->getOffset(blkSize);
710 uint8_t *blk_data = blk->data + offset;
711
712 assert(sizeof(uint64_t) >= pkt->getSize());
713
714 overwrite_mem = true;
715 // keep a copy of our possible write value, and copy what is at the
716 // memory address into the packet
717 pkt->writeData((uint8_t *)&overwrite_val);
718 pkt->setData(blk_data);
719
720 if (pkt->req->isCondSwap()) {
721 if (pkt->getSize() == sizeof(uint64_t)) {
722 condition_val64 = pkt->req->getExtraData();
723 overwrite_mem = !std::memcmp(&condition_val64, blk_data,
724 sizeof(uint64_t));
725 } else if (pkt->getSize() == sizeof(uint32_t)) {
726 condition_val32 = (uint32_t)pkt->req->getExtraData();
727 overwrite_mem = !std::memcmp(&condition_val32, blk_data,
728 sizeof(uint32_t));
729 } else
730 panic("Invalid size for conditional read/write\n");
731 }
732
733 if (overwrite_mem) {
734 std::memcpy(blk_data, &overwrite_val, pkt->getSize());
735 blk->status |= BlkDirty;
736 }
737}
738
739QueueEntry*
740BaseCache::getNextQueueEntry()
741{
742 // Check both MSHR queue and write buffer for potential requests,
743 // note that null does not mean there is no request, it could
744 // simply be that it is not ready
745 MSHR *miss_mshr = mshrQueue.getNext();
746 WriteQueueEntry *wq_entry = writeBuffer.getNext();
747
748 // If we got a write buffer request ready, first priority is a
749 // full write buffer, otherwise we favour the miss requests
750 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
751 // need to search MSHR queue for conflicting earlier miss.
752 MSHR *conflict_mshr =
753 mshrQueue.findPending(wq_entry->blkAddr,
754 wq_entry->isSecure);
755
756 if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
757 // Service misses in order until conflict is cleared.
758 return conflict_mshr;
759
760 // @todo Note that we ignore the ready time of the conflict here
761 }
762
763 // No conflicts; issue write
764 return wq_entry;
765 } else if (miss_mshr) {
766 // need to check for conflicting earlier writeback
767 WriteQueueEntry *conflict_mshr =
768 writeBuffer.findPending(miss_mshr->blkAddr,
769 miss_mshr->isSecure);
770 if (conflict_mshr) {
771 // not sure why we don't check order here... it was in the
772 // original code but commented out.
773
774 // The only way this happens is if we are
775 // doing a write and we didn't have permissions
776 // then subsequently saw a writeback (owned got evicted)
777 // We need to make sure to perform the writeback first
778 // To preserve the dirty data, then we can issue the write
779
780 // should we return wq_entry here instead? I.e. do we
781 // have to flush writes in order? I don't think so... not
782 // for Alpha anyway. Maybe for x86?
783 return conflict_mshr;
784
785 // @todo Note that we ignore the ready time of the conflict here
786 }
787
788 // No conflicts; issue read
789 return miss_mshr;
790 }
791
792 // fall through... no pending requests. Try a prefetch.
793 assert(!miss_mshr && !wq_entry);
794 if (prefetcher && mshrQueue.canPrefetch()) {
795 // If we have a miss queue slot, we can try a prefetch
796 PacketPtr pkt = prefetcher->getPacket();
797 if (pkt) {
798 Addr pf_addr = pkt->getBlockAddr(blkSize);
799 if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
800 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
801 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
802 // Update statistic on number of prefetches issued
803 // (hwpf_mshr_misses)
804 assert(pkt->req->masterId() < system->maxMasters());
805 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
806
807 // allocate an MSHR and return it, note
808 // that we send the packet straight away, so do not
809 // schedule the send
810 return allocateMissBuffer(pkt, curTick(), false);
811 } else {
812 // free the request and packet
| 1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Nikos Nikoleris
42 */
43
44/**
45 * @file
46 * Definition of BaseCache functions.
47 */
48
49#include "mem/cache/base.hh"
50
51#include "base/compiler.hh"
52#include "base/logging.hh"
53#include "debug/Cache.hh"
54#include "debug/CachePort.hh"
55#include "debug/CacheVerbose.hh"
56#include "mem/cache/mshr.hh"
57#include "mem/cache/prefetch/base.hh"
58#include "mem/cache/queue_entry.hh"
59#include "params/BaseCache.hh"
60#include "sim/core.hh"
61
62class BaseMasterPort;
63class BaseSlavePort;
64
65using namespace std;
66
67BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
68 BaseCache *_cache,
69 const std::string &_label)
70 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
71 blocked(false), mustSendRetry(false),
72 sendRetryEvent([this]{ processSendRetry(); }, _name)
73{
74}
75
76BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
77 : MemObject(p),
78 cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
79 memSidePort(p->name + ".mem_side", this, "MemSidePort"),
80 mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
81 writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
82 tags(p->tags),
83 prefetcher(p->prefetcher),
84 prefetchOnAccess(p->prefetch_on_access),
85 writebackClean(p->writeback_clean),
86 tempBlockWriteback(nullptr),
87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
88 name(), false,
89 EventBase::Delayed_Writeback_Pri),
90 blkSize(blk_size),
91 lookupLatency(p->tag_latency),
92 dataLatency(p->data_latency),
93 forwardLatency(p->tag_latency),
94 fillLatency(p->data_latency),
95 responseLatency(p->response_latency),
96 numTarget(p->tgts_per_mshr),
97 forwardSnoops(true),
98 clusivity(p->clusivity),
99 isReadOnly(p->is_read_only),
100 blocked(0),
101 order(0),
102 noTargetMSHR(nullptr),
103 missCount(p->max_miss_count),
104 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
105 system(p->system)
106{
107 // the MSHR queue has no reserve entries as we check the MSHR
108 // queue on every single allocation, whereas the write queue has
109 // as many reserve entries as we have MSHRs, since every MSHR may
110 // eventually require a writeback, and we do not check the write
111 // buffer before committing to an MSHR
112
113 // forward snoops is overridden in init() once we can query
114 // whether the connected master is actually snooping or not
115
116 tempBlock = new TempCacheBlk();
117 tempBlock->data = new uint8_t[blkSize];
118
119 tags->setCache(this);
120 if (prefetcher)
121 prefetcher->setCache(this);
122}
123
124BaseCache::~BaseCache()
125{
126 delete [] tempBlock->data;
127 delete tempBlock;
128}
129
130void
131BaseCache::CacheSlavePort::setBlocked()
132{
133 assert(!blocked);
134 DPRINTF(CachePort, "Port is blocking new requests\n");
135 blocked = true;
136 // if we already scheduled a retry in this cycle, but it has not yet
137 // happened, cancel it
138 if (sendRetryEvent.scheduled()) {
139 owner.deschedule(sendRetryEvent);
140 DPRINTF(CachePort, "Port descheduled retry\n");
141 mustSendRetry = true;
142 }
143}
144
145void
146BaseCache::CacheSlavePort::clearBlocked()
147{
148 assert(blocked);
149 DPRINTF(CachePort, "Port is accepting new requests\n");
150 blocked = false;
151 if (mustSendRetry) {
152 // @TODO: need to find a better time (next cycle?)
153 owner.schedule(sendRetryEvent, curTick() + 1);
154 }
155}
156
157void
158BaseCache::CacheSlavePort::processSendRetry()
159{
160 DPRINTF(CachePort, "Port is sending retry\n");
161
162 // reset the flag and call retry
163 mustSendRetry = false;
164 sendRetryReq();
165}
166
167Addr
168BaseCache::regenerateBlkAddr(CacheBlk* blk)
169{
170 if (blk != tempBlock) {
171 return tags->regenerateBlkAddr(blk);
172 } else {
173 return tempBlock->getAddr();
174 }
175}
176
177void
178BaseCache::init()
179{
180 if (!cpuSidePort.isConnected() || !memSidePort.isConnected())
181 fatal("Cache ports on %s are not connected\n", name());
182 cpuSidePort.sendRangeChange();
183 forwardSnoops = cpuSidePort.isSnooping();
184}
185
186BaseMasterPort &
187BaseCache::getMasterPort(const std::string &if_name, PortID idx)
188{
189 if (if_name == "mem_side") {
190 return memSidePort;
191 } else {
192 return MemObject::getMasterPort(if_name, idx);
193 }
194}
195
196BaseSlavePort &
197BaseCache::getSlavePort(const std::string &if_name, PortID idx)
198{
199 if (if_name == "cpu_side") {
200 return cpuSidePort;
201 } else {
202 return MemObject::getSlavePort(if_name, idx);
203 }
204}
205
206bool
207BaseCache::inRange(Addr addr) const
208{
209 for (const auto& r : addrRanges) {
210 if (r.contains(addr)) {
211 return true;
212 }
213 }
214 return false;
215}
216
217void
218BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
219{
220 if (pkt->needsResponse()) {
221 pkt->makeTimingResponse();
222 // @todo: Make someone pay for this
223 pkt->headerDelay = pkt->payloadDelay = 0;
224
225 // In this case we are considering request_time that takes
226 // into account the delay of the xbar, if any, and just
227 // lat, neglecting responseLatency, modelling hit latency
228 // just as lookupLatency or or the value of lat overriden
229 // by access(), that calls accessBlock() function.
230 cpuSidePort.schedTimingResp(pkt, request_time, true);
231 } else {
232 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
233 pkt->print());
234
235 // queue the packet for deletion, as the sending cache is
236 // still relying on it; if the block is found in access(),
237 // CleanEvict and Writeback messages will be deleted
238 // here as well
239 pendingDelete.reset(pkt);
240 }
241}
242
243void
244BaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
245 Tick forward_time, Tick request_time)
246{
247 if (mshr) {
248 /// MSHR hit
249 /// @note writebacks will be checked in getNextMSHR()
250 /// for any conflicting requests to the same block
251
252 //@todo remove hw_pf here
253
254 // Coalesce unless it was a software prefetch (see above).
255 if (pkt) {
256 assert(!pkt->isWriteback());
257 // CleanEvicts corresponding to blocks which have
258 // outstanding requests in MSHRs are simply sunk here
259 if (pkt->cmd == MemCmd::CleanEvict) {
260 pendingDelete.reset(pkt);
261 } else if (pkt->cmd == MemCmd::WriteClean) {
262 // A WriteClean should never coalesce with any
263 // outstanding cache maintenance requests.
264
265 // We use forward_time here because there is an
266 // uncached memory write, forwarded to WriteBuffer.
267 allocateWriteBuffer(pkt, forward_time);
268 } else {
269 DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__,
270 pkt->print());
271
272 assert(pkt->req->masterId() < system->maxMasters());
273 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
274
275 // We use forward_time here because it is the same
276 // considering new targets. We have multiple
277 // requests for the same address here. It
278 // specifies the latency to allocate an internal
279 // buffer and to schedule an event to the queued
280 // port and also takes into account the additional
281 // delay of the xbar.
282 mshr->allocateTarget(pkt, forward_time, order++,
283 allocOnFill(pkt->cmd));
284 if (mshr->getNumTargets() == numTarget) {
285 noTargetMSHR = mshr;
286 setBlocked(Blocked_NoTargets);
287 // need to be careful with this... if this mshr isn't
288 // ready yet (i.e. time > curTick()), we don't want to
289 // move it ahead of mshrs that are ready
290 // mshrQueue.moveToFront(mshr);
291 }
292 }
293 }
294 } else {
295 // no MSHR
296 assert(pkt->req->masterId() < system->maxMasters());
297 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
298
299 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) {
300 // We use forward_time here because there is an
301 // writeback or writeclean, forwarded to WriteBuffer.
302 allocateWriteBuffer(pkt, forward_time);
303 } else {
304 if (blk && blk->isValid()) {
305 // If we have a write miss to a valid block, we
306 // need to mark the block non-readable. Otherwise
307 // if we allow reads while there's an outstanding
308 // write miss, the read could return stale data
309 // out of the cache block... a more aggressive
310 // system could detect the overlap (if any) and
311 // forward data out of the MSHRs, but we don't do
312 // that yet. Note that we do need to leave the
313 // block valid so that it stays in the cache, in
314 // case we get an upgrade response (and hence no
315 // new data) when the write miss completes.
316 // As long as CPUs do proper store/load forwarding
317 // internally, and have a sufficiently weak memory
318 // model, this is probably unnecessary, but at some
319 // point it must have seemed like we needed it...
320 assert((pkt->needsWritable() && !blk->isWritable()) ||
321 pkt->req->isCacheMaintenance());
322 blk->status &= ~BlkReadable;
323 }
324 // Here we are using forward_time, modelling the latency of
325 // a miss (outbound) just as forwardLatency, neglecting the
326 // lookupLatency component.
327 allocateMissBuffer(pkt, forward_time);
328 }
329 }
330}
331
332void
333BaseCache::recvTimingReq(PacketPtr pkt)
334{
335 // anything that is merely forwarded pays for the forward latency and
336 // the delay provided by the crossbar
337 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
338
339 // We use lookupLatency here because it is used to specify the latency
340 // to access.
341 Cycles lat = lookupLatency;
342 CacheBlk *blk = nullptr;
343 bool satisfied = false;
344 {
345 PacketList writebacks;
346 // Note that lat is passed by reference here. The function
347 // access() calls accessBlock() which can modify lat value.
348 satisfied = access(pkt, blk, lat, writebacks);
349
350 // copy writebacks to write buffer here to ensure they logically
351 // proceed anything happening below
352 doWritebacks(writebacks, forward_time);
353 }
354
355 // Here we charge the headerDelay that takes into account the latencies
356 // of the bus, if the packet comes from it.
357 // The latency charged it is just lat that is the value of lookupLatency
358 // modified by access() function, or if not just lookupLatency.
359 // In case of a hit we are neglecting response latency.
360 // In case of a miss we are neglecting forward latency.
361 Tick request_time = clockEdge(lat) + pkt->headerDelay;
362 // Here we reset the timing of the packet.
363 pkt->headerDelay = pkt->payloadDelay = 0;
364 // track time of availability of next prefetch, if any
365 Tick next_pf_time = MaxTick;
366
367 if (satisfied) {
368 // if need to notify the prefetcher we have to do it before
369 // anything else as later handleTimingReqHit might turn the
370 // packet in a response
371 if (prefetcher &&
372 (prefetchOnAccess || (blk && blk->wasPrefetched()))) {
373 if (blk)
374 blk->status &= ~BlkHWPrefetched;
375
376 // Don't notify on SWPrefetch
377 if (!pkt->cmd.isSWPrefetch()) {
378 assert(!pkt->req->isCacheMaintenance());
379 next_pf_time = prefetcher->notify(pkt);
380 }
381 }
382
383 handleTimingReqHit(pkt, blk, request_time);
384 } else {
385 handleTimingReqMiss(pkt, blk, forward_time, request_time);
386
387 // We should call the prefetcher reguardless if the request is
388 // satisfied or not, reguardless if the request is in the MSHR
389 // or not. The request could be a ReadReq hit, but still not
390 // satisfied (potentially because of a prior write to the same
391 // cache line. So, even when not satisfied, there is an MSHR
392 // already allocated for this, we need to let the prefetcher
393 // know about the request
394
395 // Don't notify prefetcher on SWPrefetch or cache maintenance
396 // operations
397 if (prefetcher && pkt &&
398 !pkt->cmd.isSWPrefetch() &&
399 !pkt->req->isCacheMaintenance()) {
400 next_pf_time = prefetcher->notify(pkt);
401 }
402 }
403
404 if (next_pf_time != MaxTick) {
405 schedMemSideSendEvent(next_pf_time);
406 }
407}
408
409void
410BaseCache::handleUncacheableWriteResp(PacketPtr pkt)
411{
412 Tick completion_time = clockEdge(responseLatency) +
413 pkt->headerDelay + pkt->payloadDelay;
414
415 // Reset the bus additional time as it is now accounted for
416 pkt->headerDelay = pkt->payloadDelay = 0;
417
418 cpuSidePort.schedTimingResp(pkt, completion_time, true);
419}
420
421void
422BaseCache::recvTimingResp(PacketPtr pkt)
423{
424 assert(pkt->isResponse());
425
426 // all header delay should be paid for by the crossbar, unless
427 // this is a prefetch response from above
428 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
429 "%s saw a non-zero packet delay\n", name());
430
431 const bool is_error = pkt->isError();
432
433 if (is_error) {
434 DPRINTF(Cache, "%s: Cache received %s with error\n", __func__,
435 pkt->print());
436 }
437
438 DPRINTF(Cache, "%s: Handling response %s\n", __func__,
439 pkt->print());
440
441 // if this is a write, we should be looking at an uncacheable
442 // write
443 if (pkt->isWrite()) {
444 assert(pkt->req->isUncacheable());
445 handleUncacheableWriteResp(pkt);
446 return;
447 }
448
449 // we have dealt with any (uncacheable) writes above, from here on
450 // we know we are dealing with an MSHR due to a miss or a prefetch
451 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
452 assert(mshr);
453
454 if (mshr == noTargetMSHR) {
455 // we always clear at least one target
456 clearBlocked(Blocked_NoTargets);
457 noTargetMSHR = nullptr;
458 }
459
460 // Initial target is used just for stats
461 MSHR::Target *initial_tgt = mshr->getTarget();
462 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
463 Tick miss_latency = curTick() - initial_tgt->recvTime;
464
465 if (pkt->req->isUncacheable()) {
466 assert(pkt->req->masterId() < system->maxMasters());
467 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
468 miss_latency;
469 } else {
470 assert(pkt->req->masterId() < system->maxMasters());
471 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
472 miss_latency;
473 }
474
475 PacketList writebacks;
476
477 bool is_fill = !mshr->isForward &&
478 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
479
480 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
481
482 if (is_fill && !is_error) {
483 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
484 pkt->getAddr());
485
486 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill());
487 assert(blk != nullptr);
488 }
489
490 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) {
491 // The block was marked not readable while there was a pending
492 // cache maintenance operation, restore its flag.
493 blk->status |= BlkReadable;
494 }
495
496 if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) {
497 // If at this point the referenced block is writable and the
498 // response is not a cache invalidate, we promote targets that
499 // were deferred as we couldn't guarrantee a writable copy
500 mshr->promoteWritable();
501 }
502
503 serviceMSHRTargets(mshr, pkt, blk, writebacks);
504
505 if (mshr->promoteDeferredTargets()) {
506 // avoid later read getting stale data while write miss is
507 // outstanding.. see comment in timingAccess()
508 if (blk) {
509 blk->status &= ~BlkReadable;
510 }
511 mshrQueue.markPending(mshr);
512 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
513 } else {
514 // while we deallocate an mshr from the queue we still have to
515 // check the isFull condition before and after as we might
516 // have been using the reserved entries already
517 const bool was_full = mshrQueue.isFull();
518 mshrQueue.deallocate(mshr);
519 if (was_full && !mshrQueue.isFull()) {
520 clearBlocked(Blocked_NoMSHRs);
521 }
522
523 // Request the bus for a prefetch if this deallocation freed enough
524 // MSHRs for a prefetch to take place
525 if (prefetcher && mshrQueue.canPrefetch()) {
526 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
527 clockEdge());
528 if (next_pf_time != MaxTick)
529 schedMemSideSendEvent(next_pf_time);
530 }
531 }
532
533 // if we used temp block, check to see if its valid and then clear it out
534 if (blk == tempBlock && tempBlock->isValid()) {
535 evictBlock(blk, writebacks);
536 }
537
538 const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
539 // copy writebacks to write buffer
540 doWritebacks(writebacks, forward_time);
541
542 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
543 delete pkt;
544}
545
546
547Tick
548BaseCache::recvAtomic(PacketPtr pkt)
549{
550 // We are in atomic mode so we pay just for lookupLatency here.
551 Cycles lat = lookupLatency;
552
553 // follow the same flow as in recvTimingReq, and check if a cache
554 // above us is responding
555 if (pkt->cacheResponding() && !pkt->isClean()) {
556 assert(!pkt->req->isCacheInvalidate());
557 DPRINTF(Cache, "Cache above responding to %s: not responding\n",
558 pkt->print());
559
560 // if a cache is responding, and it had the line in Owned
561 // rather than Modified state, we need to invalidate any
562 // copies that are not on the same path to memory
563 assert(pkt->needsWritable() && !pkt->responderHadWritable());
564 lat += ticksToCycles(memSidePort.sendAtomic(pkt));
565
566 return lat * clockPeriod();
567 }
568
569 // should assert here that there are no outstanding MSHRs or
570 // writebacks... that would mean that someone used an atomic
571 // access in timing mode
572
573 CacheBlk *blk = nullptr;
574 PacketList writebacks;
575 bool satisfied = access(pkt, blk, lat, writebacks);
576
577 if (pkt->isClean() && blk && blk->isDirty()) {
578 // A cache clean opearation is looking for a dirty
579 // block. If a dirty block is encountered a WriteClean
580 // will update any copies to the path to the memory
581 // until the point of reference.
582 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
583 __func__, pkt->print(), blk->print());
584 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
585 writebacks.push_back(wb_pkt);
586 pkt->setSatisfied();
587 }
588
589 // handle writebacks resulting from the access here to ensure they
590 // logically proceed anything happening below
591 doWritebacksAtomic(writebacks);
592 assert(writebacks.empty());
593
594 if (!satisfied) {
595 lat += handleAtomicReqMiss(pkt, blk, writebacks);
596 }
597
598 // Note that we don't invoke the prefetcher at all in atomic mode.
599 // It's not clear how to do it properly, particularly for
600 // prefetchers that aggressively generate prefetch candidates and
601 // rely on bandwidth contention to throttle them; these will tend
602 // to pollute the cache in atomic mode since there is no bandwidth
603 // contention. If we ever do want to enable prefetching in atomic
604 // mode, though, this is the place to do it... see timingAccess()
605 // for an example (though we'd want to issue the prefetch(es)
606 // immediately rather than calling requestMemSideBus() as we do
607 // there).
608
609 // do any writebacks resulting from the response handling
610 doWritebacksAtomic(writebacks);
611
612 // if we used temp block, check to see if its valid and if so
613 // clear it out, but only do so after the call to recvAtomic is
614 // finished so that any downstream observers (such as a snoop
615 // filter), first see the fill, and only then see the eviction
616 if (blk == tempBlock && tempBlock->isValid()) {
617 // the atomic CPU calls recvAtomic for fetch and load/store
618 // sequentuially, and we may already have a tempBlock
619 // writeback from the fetch that we have not yet sent
620 if (tempBlockWriteback) {
621 // if that is the case, write the prevoius one back, and
622 // do not schedule any new event
623 writebackTempBlockAtomic();
624 } else {
625 // the writeback/clean eviction happens after the call to
626 // recvAtomic has finished (but before any successive
627 // calls), so that the response handling from the fill is
628 // allowed to happen first
629 schedule(writebackTempBlockAtomicEvent, curTick());
630 }
631
632 tempBlockWriteback = evictBlock(blk);
633 }
634
635 if (pkt->needsResponse()) {
636 pkt->makeAtomicResponse();
637 }
638
639 return lat * clockPeriod();
640}
641
642void
643BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
644{
645 Addr blk_addr = pkt->getBlockAddr(blkSize);
646 bool is_secure = pkt->isSecure();
647 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
648 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
649
650 pkt->pushLabel(name());
651
652 CacheBlkPrintWrapper cbpw(blk);
653
654 // Note that just because an L2/L3 has valid data doesn't mean an
655 // L1 doesn't have a more up-to-date modified copy that still
656 // needs to be found. As a result we always update the request if
657 // we have it, but only declare it satisfied if we are the owner.
658
659 // see if we have data at all (owned or otherwise)
660 bool have_data = blk && blk->isValid()
661 && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
662 blk->data);
663
664 // data we have is dirty if marked as such or if we have an
665 // in-service MSHR that is pending a modified line
666 bool have_dirty =
667 have_data && (blk->isDirty() ||
668 (mshr && mshr->inService && mshr->isPendingModified()));
669
670 bool done = have_dirty ||
671 cpuSidePort.checkFunctional(pkt) ||
672 mshrQueue.checkFunctional(pkt, blk_addr) ||
673 writeBuffer.checkFunctional(pkt, blk_addr) ||
674 memSidePort.checkFunctional(pkt);
675
676 DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(),
677 (blk && blk->isValid()) ? "valid " : "",
678 have_data ? "data " : "", done ? "done " : "");
679
680 // We're leaving the cache, so pop cache->name() label
681 pkt->popLabel();
682
683 if (done) {
684 pkt->makeResponse();
685 } else {
686 // if it came as a request from the CPU side then make sure it
687 // continues towards the memory side
688 if (from_cpu_side) {
689 memSidePort.sendFunctional(pkt);
690 } else if (cpuSidePort.isSnooping()) {
691 // if it came from the memory side, it must be a snoop request
692 // and we should only forward it if we are forwarding snoops
693 cpuSidePort.sendFunctionalSnoop(pkt);
694 }
695 }
696}
697
698
699void
700BaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
701{
702 assert(pkt->isRequest());
703
704 uint64_t overwrite_val;
705 bool overwrite_mem;
706 uint64_t condition_val64;
707 uint32_t condition_val32;
708
709 int offset = pkt->getOffset(blkSize);
710 uint8_t *blk_data = blk->data + offset;
711
712 assert(sizeof(uint64_t) >= pkt->getSize());
713
714 overwrite_mem = true;
715 // keep a copy of our possible write value, and copy what is at the
716 // memory address into the packet
717 pkt->writeData((uint8_t *)&overwrite_val);
718 pkt->setData(blk_data);
719
720 if (pkt->req->isCondSwap()) {
721 if (pkt->getSize() == sizeof(uint64_t)) {
722 condition_val64 = pkt->req->getExtraData();
723 overwrite_mem = !std::memcmp(&condition_val64, blk_data,
724 sizeof(uint64_t));
725 } else if (pkt->getSize() == sizeof(uint32_t)) {
726 condition_val32 = (uint32_t)pkt->req->getExtraData();
727 overwrite_mem = !std::memcmp(&condition_val32, blk_data,
728 sizeof(uint32_t));
729 } else
730 panic("Invalid size for conditional read/write\n");
731 }
732
733 if (overwrite_mem) {
734 std::memcpy(blk_data, &overwrite_val, pkt->getSize());
735 blk->status |= BlkDirty;
736 }
737}
738
739QueueEntry*
740BaseCache::getNextQueueEntry()
741{
742 // Check both MSHR queue and write buffer for potential requests,
743 // note that null does not mean there is no request, it could
744 // simply be that it is not ready
745 MSHR *miss_mshr = mshrQueue.getNext();
746 WriteQueueEntry *wq_entry = writeBuffer.getNext();
747
748 // If we got a write buffer request ready, first priority is a
749 // full write buffer, otherwise we favour the miss requests
750 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
751 // need to search MSHR queue for conflicting earlier miss.
752 MSHR *conflict_mshr =
753 mshrQueue.findPending(wq_entry->blkAddr,
754 wq_entry->isSecure);
755
756 if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
757 // Service misses in order until conflict is cleared.
758 return conflict_mshr;
759
760 // @todo Note that we ignore the ready time of the conflict here
761 }
762
763 // No conflicts; issue write
764 return wq_entry;
765 } else if (miss_mshr) {
766 // need to check for conflicting earlier writeback
767 WriteQueueEntry *conflict_mshr =
768 writeBuffer.findPending(miss_mshr->blkAddr,
769 miss_mshr->isSecure);
770 if (conflict_mshr) {
771 // not sure why we don't check order here... it was in the
772 // original code but commented out.
773
774 // The only way this happens is if we are
775 // doing a write and we didn't have permissions
776 // then subsequently saw a writeback (owned got evicted)
777 // We need to make sure to perform the writeback first
778 // To preserve the dirty data, then we can issue the write
779
780 // should we return wq_entry here instead? I.e. do we
781 // have to flush writes in order? I don't think so... not
782 // for Alpha anyway. Maybe for x86?
783 return conflict_mshr;
784
785 // @todo Note that we ignore the ready time of the conflict here
786 }
787
788 // No conflicts; issue read
789 return miss_mshr;
790 }
791
792 // fall through... no pending requests. Try a prefetch.
793 assert(!miss_mshr && !wq_entry);
794 if (prefetcher && mshrQueue.canPrefetch()) {
795 // If we have a miss queue slot, we can try a prefetch
796 PacketPtr pkt = prefetcher->getPacket();
797 if (pkt) {
798 Addr pf_addr = pkt->getBlockAddr(blkSize);
799 if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
800 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
801 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
802 // Update statistic on number of prefetches issued
803 // (hwpf_mshr_misses)
804 assert(pkt->req->masterId() < system->maxMasters());
805 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
806
807 // allocate an MSHR and return it, note
808 // that we send the packet straight away, so do not
809 // schedule the send
810 return allocateMissBuffer(pkt, curTick(), false);
811 } else {
812 // free the request and packet
|
813 delete pkt->req;
| |
814 delete pkt;
815 }
816 }
817 }
818
819 return nullptr;
820}
821
822void
823BaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool)
824{
825 assert(pkt->isRequest());
826
827 assert(blk && blk->isValid());
828 // Occasionally this is not true... if we are a lower-level cache
829 // satisfying a string of Read and ReadEx requests from
830 // upper-level caches, a Read will mark the block as shared but we
831 // can satisfy a following ReadEx anyway since we can rely on the
832 // Read requester(s) to have buffered the ReadEx snoop and to
833 // invalidate their blocks after receiving them.
834 // assert(!pkt->needsWritable() || blk->isWritable());
835 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
836
837 // Check RMW operations first since both isRead() and
838 // isWrite() will be true for them
839 if (pkt->cmd == MemCmd::SwapReq) {
840 cmpAndSwap(blk, pkt);
841 } else if (pkt->isWrite()) {
842 // we have the block in a writable state and can go ahead,
843 // note that the line may be also be considered writable in
844 // downstream caches along the path to memory, but always
845 // Exclusive, and never Modified
846 assert(blk->isWritable());
847 // Write or WriteLine at the first cache with block in writable state
848 if (blk->checkWrite(pkt)) {
849 pkt->writeDataToBlock(blk->data, blkSize);
850 }
851 // Always mark the line as dirty (and thus transition to the
852 // Modified state) even if we are a failed StoreCond so we
853 // supply data to any snoops that have appended themselves to
854 // this cache before knowing the store will fail.
855 blk->status |= BlkDirty;
856 DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print());
857 } else if (pkt->isRead()) {
858 if (pkt->isLLSC()) {
859 blk->trackLoadLocked(pkt);
860 }
861
862 // all read responses have a data payload
863 assert(pkt->hasRespData());
864 pkt->setDataFromBlock(blk->data, blkSize);
865 } else if (pkt->isUpgrade()) {
866 // sanity check
867 assert(!pkt->hasSharers());
868
869 if (blk->isDirty()) {
870 // we were in the Owned state, and a cache above us that
871 // has the line in Shared state needs to be made aware
872 // that the data it already has is in fact dirty
873 pkt->setCacheResponding();
874 blk->status &= ~BlkDirty;
875 }
876 } else {
877 assert(pkt->isInvalidate());
878 invalidateBlock(blk);
879 DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__,
880 pkt->print());
881 }
882}
883
884/////////////////////////////////////////////////////
885//
886// Access path: requests coming in from the CPU side
887//
888/////////////////////////////////////////////////////
889
890bool
891BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
892 PacketList &writebacks)
893{
894 // sanity check
895 assert(pkt->isRequest());
896
897 chatty_assert(!(isReadOnly && pkt->isWrite()),
898 "Should never see a write in a read-only cache %s\n",
899 name());
900
901 // Here lat is the value passed as parameter to accessBlock() function
902 // that can modify its value.
903 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
904
905 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
906 blk ? "hit " + blk->print() : "miss");
907
908 if (pkt->req->isCacheMaintenance()) {
909 // A cache maintenance operation is always forwarded to the
910 // memory below even if the block is found in dirty state.
911
912 // We defer any changes to the state of the block until we
913 // create and mark as in service the mshr for the downstream
914 // packet.
915 return false;
916 }
917
918 if (pkt->isEviction()) {
919 // We check for presence of block in above caches before issuing
920 // Writeback or CleanEvict to write buffer. Therefore the only
921 // possible cases can be of a CleanEvict packet coming from above
922 // encountering a Writeback generated in this cache peer cache and
923 // waiting in the write buffer. Cases of upper level peer caches
924 // generating CleanEvict and Writeback or simply CleanEvict and
925 // CleanEvict almost simultaneously will be caught by snoops sent out
926 // by crossbar.
927 WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(),
928 pkt->isSecure());
929 if (wb_entry) {
930 assert(wb_entry->getNumTargets() == 1);
931 PacketPtr wbPkt = wb_entry->getTarget()->pkt;
932 assert(wbPkt->isWriteback());
933
934 if (pkt->isCleanEviction()) {
935 // The CleanEvict and WritebackClean snoops into other
936 // peer caches of the same level while traversing the
937 // crossbar. If a copy of the block is found, the
938 // packet is deleted in the crossbar. Hence, none of
939 // the other upper level caches connected to this
940 // cache have the block, so we can clear the
941 // BLOCK_CACHED flag in the Writeback if set and
942 // discard the CleanEvict by returning true.
943 wbPkt->clearBlockCached();
944 return true;
945 } else {
946 assert(pkt->cmd == MemCmd::WritebackDirty);
947 // Dirty writeback from above trumps our clean
948 // writeback... discard here
949 // Note: markInService will remove entry from writeback buffer.
950 markInService(wb_entry);
951 delete wbPkt;
952 }
953 }
954 }
955
956 // Writeback handling is special case. We can write the block into
957 // the cache without having a writeable copy (or any copy at all).
958 if (pkt->isWriteback()) {
959 assert(blkSize == pkt->getSize());
960
961 // we could get a clean writeback while we are having
962 // outstanding accesses to a block, do the simple thing for
963 // now and drop the clean writeback so that we do not upset
964 // any ordering/decisions about ownership already taken
965 if (pkt->cmd == MemCmd::WritebackClean &&
966 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
967 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
968 "dropping\n", pkt->getAddr());
969 return true;
970 }
971
972 if (!blk) {
973 // need to do a replacement
974 blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
975 if (!blk) {
976 // no replaceable block available: give up, fwd to next level.
977 incMissCount(pkt);
978 return false;
979 }
980 tags->insertBlock(pkt, blk);
981
982 blk->status |= (BlkValid | BlkReadable);
983 }
984 // only mark the block dirty if we got a writeback command,
985 // and leave it as is for a clean writeback
986 if (pkt->cmd == MemCmd::WritebackDirty) {
987 // TODO: the coherent cache can assert(!blk->isDirty());
988 blk->status |= BlkDirty;
989 }
990 // if the packet does not have sharers, it is passing
991 // writable, and we got the writeback in Modified or Exclusive
992 // state, if not we are in the Owned or Shared state
993 if (!pkt->hasSharers()) {
994 blk->status |= BlkWritable;
995 }
996 // nothing else to do; writeback doesn't expect response
997 assert(!pkt->needsResponse());
998 pkt->writeDataToBlock(blk->data, blkSize);
999 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1000 incHitCount(pkt);
1001 // populate the time when the block will be ready to access.
1002 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1003 pkt->payloadDelay;
1004 return true;
1005 } else if (pkt->cmd == MemCmd::CleanEvict) {
1006 if (blk) {
1007 // Found the block in the tags, need to stop CleanEvict from
1008 // propagating further down the hierarchy. Returning true will
1009 // treat the CleanEvict like a satisfied write request and delete
1010 // it.
1011 return true;
1012 }
1013 // We didn't find the block here, propagate the CleanEvict further
1014 // down the memory hierarchy. Returning false will treat the CleanEvict
1015 // like a Writeback which could not find a replaceable block so has to
1016 // go to next level.
1017 return false;
1018 } else if (pkt->cmd == MemCmd::WriteClean) {
1019 // WriteClean handling is a special case. We can allocate a
1020 // block directly if it doesn't exist and we can update the
1021 // block immediately. The WriteClean transfers the ownership
1022 // of the block as well.
1023 assert(blkSize == pkt->getSize());
1024
1025 if (!blk) {
1026 if (pkt->writeThrough()) {
1027 // if this is a write through packet, we don't try to
1028 // allocate if the block is not present
1029 return false;
1030 } else {
1031 // a writeback that misses needs to allocate a new block
1032 blk = allocateBlock(pkt->getAddr(), pkt->isSecure(),
1033 writebacks);
1034 if (!blk) {
1035 // no replaceable block available: give up, fwd to
1036 // next level.
1037 incMissCount(pkt);
1038 return false;
1039 }
1040 tags->insertBlock(pkt, blk);
1041
1042 blk->status |= (BlkValid | BlkReadable);
1043 }
1044 }
1045
1046 // at this point either this is a writeback or a write-through
1047 // write clean operation and the block is already in this
1048 // cache, we need to update the data and the block flags
1049 assert(blk);
1050 // TODO: the coherent cache can assert(!blk->isDirty());
1051 if (!pkt->writeThrough()) {
1052 blk->status |= BlkDirty;
1053 }
1054 // nothing else to do; writeback doesn't expect response
1055 assert(!pkt->needsResponse());
1056 pkt->writeDataToBlock(blk->data, blkSize);
1057 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1058
1059 incHitCount(pkt);
1060 // populate the time when the block will be ready to access.
1061 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1062 pkt->payloadDelay;
1063 // if this a write-through packet it will be sent to cache
1064 // below
1065 return !pkt->writeThrough();
1066 } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
1067 blk->isReadable())) {
1068 // OK to satisfy access
1069 incHitCount(pkt);
1070 satisfyRequest(pkt, blk);
1071 maintainClusivity(pkt->fromCache(), blk);
1072
1073 return true;
1074 }
1075
1076 // Can't satisfy access normally... either no block (blk == nullptr)
1077 // or have block but need writable
1078
1079 incMissCount(pkt);
1080
1081 if (!blk && pkt->isLLSC() && pkt->isWrite()) {
1082 // complete miss on store conditional... just give up now
1083 pkt->req->setExtraData(0);
1084 return true;
1085 }
1086
1087 return false;
1088}
1089
1090void
1091BaseCache::maintainClusivity(bool from_cache, CacheBlk *blk)
1092{
1093 if (from_cache && blk && blk->isValid() && !blk->isDirty() &&
1094 clusivity == Enums::mostly_excl) {
1095 // if we have responded to a cache, and our block is still
1096 // valid, but not dirty, and this cache is mostly exclusive
1097 // with respect to the cache above, drop the block
1098 invalidateBlock(blk);
1099 }
1100}
1101
1102CacheBlk*
1103BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
1104 bool allocate)
1105{
1106 assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq);
1107 Addr addr = pkt->getAddr();
1108 bool is_secure = pkt->isSecure();
1109#if TRACING_ON
1110 CacheBlk::State old_state = blk ? blk->status : 0;
1111#endif
1112
1113 // When handling a fill, we should have no writes to this line.
1114 assert(addr == pkt->getBlockAddr(blkSize));
1115 assert(!writeBuffer.findMatch(addr, is_secure));
1116
1117 if (!blk) {
1118 // better have read new data...
1119 assert(pkt->hasData());
1120
1121 // only read responses and write-line requests have data;
1122 // note that we don't write the data here for write-line - that
1123 // happens in the subsequent call to satisfyRequest
1124 assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq);
1125
1126 // need to do a replacement if allocating, otherwise we stick
1127 // with the temporary storage
1128 blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr;
1129
1130 if (!blk) {
1131 // No replaceable block or a mostly exclusive
1132 // cache... just use temporary storage to complete the
1133 // current request and then get rid of it
1134 assert(!tempBlock->isValid());
1135 blk = tempBlock;
1136 tempBlock->insert(addr, is_secure);
1137 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
1138 is_secure ? "s" : "ns");
1139 } else {
1140 tags->insertBlock(pkt, blk);
1141 }
1142
1143 // we should never be overwriting a valid block
1144 assert(!blk->isValid());
1145 } else {
1146 // existing block... probably an upgrade
1147 assert(regenerateBlkAddr(blk) == addr);
1148 assert(blk->isSecure() == is_secure);
1149 // either we're getting new data or the block should already be valid
1150 assert(pkt->hasData() || blk->isValid());
1151 // don't clear block status... if block is already dirty we
1152 // don't want to lose that
1153 }
1154
1155 blk->status |= BlkValid | BlkReadable;
1156
1157 // sanity check for whole-line writes, which should always be
1158 // marked as writable as part of the fill, and then later marked
1159 // dirty as part of satisfyRequest
1160 if (pkt->cmd == MemCmd::WriteLineReq) {
1161 assert(!pkt->hasSharers());
1162 }
1163
1164 // here we deal with setting the appropriate state of the line,
1165 // and we start by looking at the hasSharers flag, and ignore the
1166 // cacheResponding flag (normally signalling dirty data) if the
1167 // packet has sharers, thus the line is never allocated as Owned
1168 // (dirty but not writable), and always ends up being either
1169 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1170 // for more details
1171 if (!pkt->hasSharers()) {
1172 // we could get a writable line from memory (rather than a
1173 // cache) even in a read-only cache, note that we set this bit
1174 // even for a read-only cache, possibly revisit this decision
1175 blk->status |= BlkWritable;
1176
1177 // check if we got this via cache-to-cache transfer (i.e., from a
1178 // cache that had the block in Modified or Owned state)
1179 if (pkt->cacheResponding()) {
1180 // we got the block in Modified state, and invalidated the
1181 // owners copy
1182 blk->status |= BlkDirty;
1183
1184 chatty_assert(!isReadOnly, "Should never see dirty snoop response "
1185 "in read-only cache %s\n", name());
1186 }
1187 }
1188
1189 DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
1190 addr, is_secure ? "s" : "ns", old_state, blk->print());
1191
1192 // if we got new data, copy it in (checking for a read response
1193 // and a response that has data is the same in the end)
1194 if (pkt->isRead()) {
1195 // sanity checks
1196 assert(pkt->hasData());
1197 assert(pkt->getSize() == blkSize);
1198
1199 pkt->writeDataToBlock(blk->data, blkSize);
1200 }
1201 // We pay for fillLatency here.
1202 blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
1203 pkt->payloadDelay;
1204
1205 return blk;
1206}
1207
1208CacheBlk*
1209BaseCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
1210{
1211 // Find replacement victim
1212 std::vector<CacheBlk*> evict_blks;
1213 CacheBlk *victim = tags->findVictim(addr, is_secure, evict_blks);
1214
1215 // It is valid to return nullptr if there is no victim
1216 if (!victim)
1217 return nullptr;
1218
1219 // Check for transient state allocations. If any of the entries listed
1220 // for eviction has a transient state, the allocation fails
1221 for (const auto& blk : evict_blks) {
1222 if (blk->isValid()) {
1223 Addr repl_addr = regenerateBlkAddr(blk);
1224 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
1225 if (repl_mshr) {
1226 // must be an outstanding upgrade or clean request
1227 // on a block we're about to replace...
1228 assert((!blk->isWritable() && repl_mshr->needsWritable()) ||
1229 repl_mshr->isCleaning());
1230
1231 // too hard to replace block with transient state
1232 // allocation failed, block not inserted
1233 return nullptr;
1234 }
1235 }
1236 }
1237
1238 // The victim will be replaced by a new entry, so increase the replacement
1239 // counter if a valid block is being replaced
1240 if (victim->isValid()) {
1241 DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
1242 "(%s): %s\n", regenerateBlkAddr(victim),
1243 victim->isSecure() ? "s" : "ns",
1244 addr, is_secure ? "s" : "ns",
1245 victim->isDirty() ? "writeback" : "clean");
1246
1247 replacements++;
1248 }
1249
1250 // Evict valid blocks associated to this victim block
1251 for (const auto& blk : evict_blks) {
1252 if (blk->isValid()) {
1253 if (blk->wasPrefetched()) {
1254 unusedPrefetches++;
1255 }
1256
1257 evictBlock(blk, writebacks);
1258 }
1259 }
1260
1261 return victim;
1262}
1263
1264void
1265BaseCache::invalidateBlock(CacheBlk *blk)
1266{
1267 if (blk != tempBlock)
1268 tags->invalidate(blk);
1269 blk->invalidate();
1270}
1271
1272PacketPtr
1273BaseCache::writebackBlk(CacheBlk *blk)
1274{
1275 chatty_assert(!isReadOnly || writebackClean,
1276 "Writeback from read-only cache");
1277 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
1278
1279 writebacks[Request::wbMasterId]++;
1280
| 813 delete pkt;
814 }
815 }
816 }
817
818 return nullptr;
819}
820
821void
822BaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool)
823{
824 assert(pkt->isRequest());
825
826 assert(blk && blk->isValid());
827 // Occasionally this is not true... if we are a lower-level cache
828 // satisfying a string of Read and ReadEx requests from
829 // upper-level caches, a Read will mark the block as shared but we
830 // can satisfy a following ReadEx anyway since we can rely on the
831 // Read requester(s) to have buffered the ReadEx snoop and to
832 // invalidate their blocks after receiving them.
833 // assert(!pkt->needsWritable() || blk->isWritable());
834 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
835
836 // Check RMW operations first since both isRead() and
837 // isWrite() will be true for them
838 if (pkt->cmd == MemCmd::SwapReq) {
839 cmpAndSwap(blk, pkt);
840 } else if (pkt->isWrite()) {
841 // we have the block in a writable state and can go ahead,
842 // note that the line may be also be considered writable in
843 // downstream caches along the path to memory, but always
844 // Exclusive, and never Modified
845 assert(blk->isWritable());
846 // Write or WriteLine at the first cache with block in writable state
847 if (blk->checkWrite(pkt)) {
848 pkt->writeDataToBlock(blk->data, blkSize);
849 }
850 // Always mark the line as dirty (and thus transition to the
851 // Modified state) even if we are a failed StoreCond so we
852 // supply data to any snoops that have appended themselves to
853 // this cache before knowing the store will fail.
854 blk->status |= BlkDirty;
855 DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print());
856 } else if (pkt->isRead()) {
857 if (pkt->isLLSC()) {
858 blk->trackLoadLocked(pkt);
859 }
860
861 // all read responses have a data payload
862 assert(pkt->hasRespData());
863 pkt->setDataFromBlock(blk->data, blkSize);
864 } else if (pkt->isUpgrade()) {
865 // sanity check
866 assert(!pkt->hasSharers());
867
868 if (blk->isDirty()) {
869 // we were in the Owned state, and a cache above us that
870 // has the line in Shared state needs to be made aware
871 // that the data it already has is in fact dirty
872 pkt->setCacheResponding();
873 blk->status &= ~BlkDirty;
874 }
875 } else {
876 assert(pkt->isInvalidate());
877 invalidateBlock(blk);
878 DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__,
879 pkt->print());
880 }
881}
882
883/////////////////////////////////////////////////////
884//
885// Access path: requests coming in from the CPU side
886//
887/////////////////////////////////////////////////////
888
889bool
890BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
891 PacketList &writebacks)
892{
893 // sanity check
894 assert(pkt->isRequest());
895
896 chatty_assert(!(isReadOnly && pkt->isWrite()),
897 "Should never see a write in a read-only cache %s\n",
898 name());
899
900 // Here lat is the value passed as parameter to accessBlock() function
901 // that can modify its value.
902 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
903
904 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
905 blk ? "hit " + blk->print() : "miss");
906
907 if (pkt->req->isCacheMaintenance()) {
908 // A cache maintenance operation is always forwarded to the
909 // memory below even if the block is found in dirty state.
910
911 // We defer any changes to the state of the block until we
912 // create and mark as in service the mshr for the downstream
913 // packet.
914 return false;
915 }
916
917 if (pkt->isEviction()) {
918 // We check for presence of block in above caches before issuing
919 // Writeback or CleanEvict to write buffer. Therefore the only
920 // possible cases can be of a CleanEvict packet coming from above
921 // encountering a Writeback generated in this cache peer cache and
922 // waiting in the write buffer. Cases of upper level peer caches
923 // generating CleanEvict and Writeback or simply CleanEvict and
924 // CleanEvict almost simultaneously will be caught by snoops sent out
925 // by crossbar.
926 WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(),
927 pkt->isSecure());
928 if (wb_entry) {
929 assert(wb_entry->getNumTargets() == 1);
930 PacketPtr wbPkt = wb_entry->getTarget()->pkt;
931 assert(wbPkt->isWriteback());
932
933 if (pkt->isCleanEviction()) {
934 // The CleanEvict and WritebackClean snoops into other
935 // peer caches of the same level while traversing the
936 // crossbar. If a copy of the block is found, the
937 // packet is deleted in the crossbar. Hence, none of
938 // the other upper level caches connected to this
939 // cache have the block, so we can clear the
940 // BLOCK_CACHED flag in the Writeback if set and
941 // discard the CleanEvict by returning true.
942 wbPkt->clearBlockCached();
943 return true;
944 } else {
945 assert(pkt->cmd == MemCmd::WritebackDirty);
946 // Dirty writeback from above trumps our clean
947 // writeback... discard here
948 // Note: markInService will remove entry from writeback buffer.
949 markInService(wb_entry);
950 delete wbPkt;
951 }
952 }
953 }
954
955 // Writeback handling is special case. We can write the block into
956 // the cache without having a writeable copy (or any copy at all).
957 if (pkt->isWriteback()) {
958 assert(blkSize == pkt->getSize());
959
960 // we could get a clean writeback while we are having
961 // outstanding accesses to a block, do the simple thing for
962 // now and drop the clean writeback so that we do not upset
963 // any ordering/decisions about ownership already taken
964 if (pkt->cmd == MemCmd::WritebackClean &&
965 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
966 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
967 "dropping\n", pkt->getAddr());
968 return true;
969 }
970
971 if (!blk) {
972 // need to do a replacement
973 blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
974 if (!blk) {
975 // no replaceable block available: give up, fwd to next level.
976 incMissCount(pkt);
977 return false;
978 }
979 tags->insertBlock(pkt, blk);
980
981 blk->status |= (BlkValid | BlkReadable);
982 }
983 // only mark the block dirty if we got a writeback command,
984 // and leave it as is for a clean writeback
985 if (pkt->cmd == MemCmd::WritebackDirty) {
986 // TODO: the coherent cache can assert(!blk->isDirty());
987 blk->status |= BlkDirty;
988 }
989 // if the packet does not have sharers, it is passing
990 // writable, and we got the writeback in Modified or Exclusive
991 // state, if not we are in the Owned or Shared state
992 if (!pkt->hasSharers()) {
993 blk->status |= BlkWritable;
994 }
995 // nothing else to do; writeback doesn't expect response
996 assert(!pkt->needsResponse());
997 pkt->writeDataToBlock(blk->data, blkSize);
998 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
999 incHitCount(pkt);
1000 // populate the time when the block will be ready to access.
1001 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1002 pkt->payloadDelay;
1003 return true;
1004 } else if (pkt->cmd == MemCmd::CleanEvict) {
1005 if (blk) {
1006 // Found the block in the tags, need to stop CleanEvict from
1007 // propagating further down the hierarchy. Returning true will
1008 // treat the CleanEvict like a satisfied write request and delete
1009 // it.
1010 return true;
1011 }
1012 // We didn't find the block here, propagate the CleanEvict further
1013 // down the memory hierarchy. Returning false will treat the CleanEvict
1014 // like a Writeback which could not find a replaceable block so has to
1015 // go to next level.
1016 return false;
1017 } else if (pkt->cmd == MemCmd::WriteClean) {
1018 // WriteClean handling is a special case. We can allocate a
1019 // block directly if it doesn't exist and we can update the
1020 // block immediately. The WriteClean transfers the ownership
1021 // of the block as well.
1022 assert(blkSize == pkt->getSize());
1023
1024 if (!blk) {
1025 if (pkt->writeThrough()) {
1026 // if this is a write through packet, we don't try to
1027 // allocate if the block is not present
1028 return false;
1029 } else {
1030 // a writeback that misses needs to allocate a new block
1031 blk = allocateBlock(pkt->getAddr(), pkt->isSecure(),
1032 writebacks);
1033 if (!blk) {
1034 // no replaceable block available: give up, fwd to
1035 // next level.
1036 incMissCount(pkt);
1037 return false;
1038 }
1039 tags->insertBlock(pkt, blk);
1040
1041 blk->status |= (BlkValid | BlkReadable);
1042 }
1043 }
1044
1045 // at this point either this is a writeback or a write-through
1046 // write clean operation and the block is already in this
1047 // cache, we need to update the data and the block flags
1048 assert(blk);
1049 // TODO: the coherent cache can assert(!blk->isDirty());
1050 if (!pkt->writeThrough()) {
1051 blk->status |= BlkDirty;
1052 }
1053 // nothing else to do; writeback doesn't expect response
1054 assert(!pkt->needsResponse());
1055 pkt->writeDataToBlock(blk->data, blkSize);
1056 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1057
1058 incHitCount(pkt);
1059 // populate the time when the block will be ready to access.
1060 blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1061 pkt->payloadDelay;
1062 // if this a write-through packet it will be sent to cache
1063 // below
1064 return !pkt->writeThrough();
1065 } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
1066 blk->isReadable())) {
1067 // OK to satisfy access
1068 incHitCount(pkt);
1069 satisfyRequest(pkt, blk);
1070 maintainClusivity(pkt->fromCache(), blk);
1071
1072 return true;
1073 }
1074
1075 // Can't satisfy access normally... either no block (blk == nullptr)
1076 // or have block but need writable
1077
1078 incMissCount(pkt);
1079
1080 if (!blk && pkt->isLLSC() && pkt->isWrite()) {
1081 // complete miss on store conditional... just give up now
1082 pkt->req->setExtraData(0);
1083 return true;
1084 }
1085
1086 return false;
1087}
1088
1089void
1090BaseCache::maintainClusivity(bool from_cache, CacheBlk *blk)
1091{
1092 if (from_cache && blk && blk->isValid() && !blk->isDirty() &&
1093 clusivity == Enums::mostly_excl) {
1094 // if we have responded to a cache, and our block is still
1095 // valid, but not dirty, and this cache is mostly exclusive
1096 // with respect to the cache above, drop the block
1097 invalidateBlock(blk);
1098 }
1099}
1100
1101CacheBlk*
1102BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
1103 bool allocate)
1104{
1105 assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq);
1106 Addr addr = pkt->getAddr();
1107 bool is_secure = pkt->isSecure();
1108#if TRACING_ON
1109 CacheBlk::State old_state = blk ? blk->status : 0;
1110#endif
1111
1112 // When handling a fill, we should have no writes to this line.
1113 assert(addr == pkt->getBlockAddr(blkSize));
1114 assert(!writeBuffer.findMatch(addr, is_secure));
1115
1116 if (!blk) {
1117 // better have read new data...
1118 assert(pkt->hasData());
1119
1120 // only read responses and write-line requests have data;
1121 // note that we don't write the data here for write-line - that
1122 // happens in the subsequent call to satisfyRequest
1123 assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq);
1124
1125 // need to do a replacement if allocating, otherwise we stick
1126 // with the temporary storage
1127 blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr;
1128
1129 if (!blk) {
1130 // No replaceable block or a mostly exclusive
1131 // cache... just use temporary storage to complete the
1132 // current request and then get rid of it
1133 assert(!tempBlock->isValid());
1134 blk = tempBlock;
1135 tempBlock->insert(addr, is_secure);
1136 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
1137 is_secure ? "s" : "ns");
1138 } else {
1139 tags->insertBlock(pkt, blk);
1140 }
1141
1142 // we should never be overwriting a valid block
1143 assert(!blk->isValid());
1144 } else {
1145 // existing block... probably an upgrade
1146 assert(regenerateBlkAddr(blk) == addr);
1147 assert(blk->isSecure() == is_secure);
1148 // either we're getting new data or the block should already be valid
1149 assert(pkt->hasData() || blk->isValid());
1150 // don't clear block status... if block is already dirty we
1151 // don't want to lose that
1152 }
1153
1154 blk->status |= BlkValid | BlkReadable;
1155
1156 // sanity check for whole-line writes, which should always be
1157 // marked as writable as part of the fill, and then later marked
1158 // dirty as part of satisfyRequest
1159 if (pkt->cmd == MemCmd::WriteLineReq) {
1160 assert(!pkt->hasSharers());
1161 }
1162
1163 // here we deal with setting the appropriate state of the line,
1164 // and we start by looking at the hasSharers flag, and ignore the
1165 // cacheResponding flag (normally signalling dirty data) if the
1166 // packet has sharers, thus the line is never allocated as Owned
1167 // (dirty but not writable), and always ends up being either
1168 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1169 // for more details
1170 if (!pkt->hasSharers()) {
1171 // we could get a writable line from memory (rather than a
1172 // cache) even in a read-only cache, note that we set this bit
1173 // even for a read-only cache, possibly revisit this decision
1174 blk->status |= BlkWritable;
1175
1176 // check if we got this via cache-to-cache transfer (i.e., from a
1177 // cache that had the block in Modified or Owned state)
1178 if (pkt->cacheResponding()) {
1179 // we got the block in Modified state, and invalidated the
1180 // owners copy
1181 blk->status |= BlkDirty;
1182
1183 chatty_assert(!isReadOnly, "Should never see dirty snoop response "
1184 "in read-only cache %s\n", name());
1185 }
1186 }
1187
1188 DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
1189 addr, is_secure ? "s" : "ns", old_state, blk->print());
1190
1191 // if we got new data, copy it in (checking for a read response
1192 // and a response that has data is the same in the end)
1193 if (pkt->isRead()) {
1194 // sanity checks
1195 assert(pkt->hasData());
1196 assert(pkt->getSize() == blkSize);
1197
1198 pkt->writeDataToBlock(blk->data, blkSize);
1199 }
1200 // We pay for fillLatency here.
1201 blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
1202 pkt->payloadDelay;
1203
1204 return blk;
1205}
1206
1207CacheBlk*
1208BaseCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
1209{
1210 // Find replacement victim
1211 std::vector<CacheBlk*> evict_blks;
1212 CacheBlk *victim = tags->findVictim(addr, is_secure, evict_blks);
1213
1214 // It is valid to return nullptr if there is no victim
1215 if (!victim)
1216 return nullptr;
1217
1218 // Check for transient state allocations. If any of the entries listed
1219 // for eviction has a transient state, the allocation fails
1220 for (const auto& blk : evict_blks) {
1221 if (blk->isValid()) {
1222 Addr repl_addr = regenerateBlkAddr(blk);
1223 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
1224 if (repl_mshr) {
1225 // must be an outstanding upgrade or clean request
1226 // on a block we're about to replace...
1227 assert((!blk->isWritable() && repl_mshr->needsWritable()) ||
1228 repl_mshr->isCleaning());
1229
1230 // too hard to replace block with transient state
1231 // allocation failed, block not inserted
1232 return nullptr;
1233 }
1234 }
1235 }
1236
1237 // The victim will be replaced by a new entry, so increase the replacement
1238 // counter if a valid block is being replaced
1239 if (victim->isValid()) {
1240 DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
1241 "(%s): %s\n", regenerateBlkAddr(victim),
1242 victim->isSecure() ? "s" : "ns",
1243 addr, is_secure ? "s" : "ns",
1244 victim->isDirty() ? "writeback" : "clean");
1245
1246 replacements++;
1247 }
1248
1249 // Evict valid blocks associated to this victim block
1250 for (const auto& blk : evict_blks) {
1251 if (blk->isValid()) {
1252 if (blk->wasPrefetched()) {
1253 unusedPrefetches++;
1254 }
1255
1256 evictBlock(blk, writebacks);
1257 }
1258 }
1259
1260 return victim;
1261}
1262
1263void
1264BaseCache::invalidateBlock(CacheBlk *blk)
1265{
1266 if (blk != tempBlock)
1267 tags->invalidate(blk);
1268 blk->invalidate();
1269}
1270
1271PacketPtr
1272BaseCache::writebackBlk(CacheBlk *blk)
1273{
1274 chatty_assert(!isReadOnly || writebackClean,
1275 "Writeback from read-only cache");
1276 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
1277
1278 writebacks[Request::wbMasterId]++;
1279
|
1281 RequestPtr req = new Request(regenerateBlkAddr(blk), blkSize, 0,
1282 Request::wbMasterId);
| 1280 RequestPtr req = std::make_shared<Request>(
1281 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId);
1282
|
1283 if (blk->isSecure())
1284 req->setFlags(Request::SECURE);
1285
1286 req->taskId(blk->task_id);
1287
1288 PacketPtr pkt =
1289 new Packet(req, blk->isDirty() ?
1290 MemCmd::WritebackDirty : MemCmd::WritebackClean);
1291
1292 DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n",
1293 pkt->print(), blk->isWritable(), blk->isDirty());
1294
1295 if (blk->isWritable()) {
1296 // not asserting shared means we pass the block in modified
1297 // state, mark our own block non-writeable
1298 blk->status &= ~BlkWritable;
1299 } else {
1300 // we are in the Owned state, tell the receiver
1301 pkt->setHasSharers();
1302 }
1303
1304 // make sure the block is not marked dirty
1305 blk->status &= ~BlkDirty;
1306
1307 pkt->allocate();
1308 pkt->setDataFromBlock(blk->data, blkSize);
1309
1310 return pkt;
1311}
1312
1313PacketPtr
1314BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
1315{
| 1283 if (blk->isSecure())
1284 req->setFlags(Request::SECURE);
1285
1286 req->taskId(blk->task_id);
1287
1288 PacketPtr pkt =
1289 new Packet(req, blk->isDirty() ?
1290 MemCmd::WritebackDirty : MemCmd::WritebackClean);
1291
1292 DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n",
1293 pkt->print(), blk->isWritable(), blk->isDirty());
1294
1295 if (blk->isWritable()) {
1296 // not asserting shared means we pass the block in modified
1297 // state, mark our own block non-writeable
1298 blk->status &= ~BlkWritable;
1299 } else {
1300 // we are in the Owned state, tell the receiver
1301 pkt->setHasSharers();
1302 }
1303
1304 // make sure the block is not marked dirty
1305 blk->status &= ~BlkDirty;
1306
1307 pkt->allocate();
1308 pkt->setDataFromBlock(blk->data, blkSize);
1309
1310 return pkt;
1311}
1312
1313PacketPtr
1314BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
1315{
|
1316 RequestPtr req = new Request(regenerateBlkAddr(blk), blkSize, 0,
1317 Request::wbMasterId);
| 1316 RequestPtr req = std::make_shared<Request>(
1317 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId);
1318
|
1318 if (blk->isSecure()) {
1319 req->setFlags(Request::SECURE);
1320 }
1321 req->taskId(blk->task_id);
1322
1323 PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id);
1324
1325 if (dest) {
1326 req->setFlags(dest);
1327 pkt->setWriteThrough();
1328 }
1329
1330 DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(),
1331 blk->isWritable(), blk->isDirty());
1332
1333 if (blk->isWritable()) {
1334 // not asserting shared means we pass the block in modified
1335 // state, mark our own block non-writeable
1336 blk->status &= ~BlkWritable;
1337 } else {
1338 // we are in the Owned state, tell the receiver
1339 pkt->setHasSharers();
1340 }
1341
1342 // make sure the block is not marked dirty
1343 blk->status &= ~BlkDirty;
1344
1345 pkt->allocate();
1346 pkt->setDataFromBlock(blk->data, blkSize);
1347
1348 return pkt;
1349}
1350
1351
1352void
1353BaseCache::memWriteback()
1354{
1355 tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); });
1356}
1357
1358void
1359BaseCache::memInvalidate()
1360{
1361 tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); });
1362}
1363
1364bool
1365BaseCache::isDirty() const
1366{
1367 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); });
1368}
1369
1370void
1371BaseCache::writebackVisitor(CacheBlk &blk)
1372{
1373 if (blk.isDirty()) {
1374 assert(blk.isValid());
1375
| 1319 if (blk->isSecure()) {
1320 req->setFlags(Request::SECURE);
1321 }
1322 req->taskId(blk->task_id);
1323
1324 PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id);
1325
1326 if (dest) {
1327 req->setFlags(dest);
1328 pkt->setWriteThrough();
1329 }
1330
1331 DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(),
1332 blk->isWritable(), blk->isDirty());
1333
1334 if (blk->isWritable()) {
1335 // not asserting shared means we pass the block in modified
1336 // state, mark our own block non-writeable
1337 blk->status &= ~BlkWritable;
1338 } else {
1339 // we are in the Owned state, tell the receiver
1340 pkt->setHasSharers();
1341 }
1342
1343 // make sure the block is not marked dirty
1344 blk->status &= ~BlkDirty;
1345
1346 pkt->allocate();
1347 pkt->setDataFromBlock(blk->data, blkSize);
1348
1349 return pkt;
1350}
1351
1352
1353void
1354BaseCache::memWriteback()
1355{
1356 tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); });
1357}
1358
1359void
1360BaseCache::memInvalidate()
1361{
1362 tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); });
1363}
1364
1365bool
1366BaseCache::isDirty() const
1367{
1368 return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); });
1369}
1370
1371void
1372BaseCache::writebackVisitor(CacheBlk &blk)
1373{
1374 if (blk.isDirty()) {
1375 assert(blk.isValid());
1376
|
1376 Request request(regenerateBlkAddr(&blk),
1377 blkSize, 0, Request::funcMasterId);
1378 request.taskId(blk.task_id);
| 1377 RequestPtr request = std::make_shared<Request>(
1378 regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId);
1379
1380 request->taskId(blk.task_id);
|
1379 if (blk.isSecure()) {
| 1381 if (blk.isSecure()) {
|
1380 request.setFlags(Request::SECURE);
| 1382 request->setFlags(Request::SECURE);
|
1381 }
1382
| 1383 }
1384
|
1383 Packet packet(&request, MemCmd::WriteReq);
| 1385 Packet packet(request, MemCmd::WriteReq);
|
1384 packet.dataStatic(blk.data);
1385
1386 memSidePort.sendFunctional(&packet);
1387
1388 blk.status &= ~BlkDirty;
1389 }
1390}
1391
1392void
1393BaseCache::invalidateVisitor(CacheBlk &blk)
1394{
1395 if (blk.isDirty())
1396 warn_once("Invalidating dirty cache lines. " \
1397 "Expect things to break.\n");
1398
1399 if (blk.isValid()) {
1400 assert(!blk.isDirty());
1401 invalidateBlock(&blk);
1402 }
1403}
1404
1405Tick
1406BaseCache::nextQueueReadyTime() const
1407{
1408 Tick nextReady = std::min(mshrQueue.nextReadyTime(),
1409 writeBuffer.nextReadyTime());
1410
1411 // Don't signal prefetch ready time if no MSHRs available
1412 // Will signal once enoguh MSHRs are deallocated
1413 if (prefetcher && mshrQueue.canPrefetch()) {
1414 nextReady = std::min(nextReady,
1415 prefetcher->nextPrefetchReadyTime());
1416 }
1417
1418 return nextReady;
1419}
1420
1421
1422bool
1423BaseCache::sendMSHRQueuePacket(MSHR* mshr)
1424{
1425 assert(mshr);
1426
1427 // use request from 1st target
1428 PacketPtr tgt_pkt = mshr->getTarget()->pkt;
1429
1430 DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print());
1431
1432 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
1433
1434 // either a prefetch that is not present upstream, or a normal
1435 // MSHR request, proceed to get the packet to send downstream
1436 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
1437
1438 mshr->isForward = (pkt == nullptr);
1439
1440 if (mshr->isForward) {
1441 // not a cache block request, but a response is expected
1442 // make copy of current packet to forward, keep current
1443 // copy for response handling
1444 pkt = new Packet(tgt_pkt, false, true);
1445 assert(!pkt->isWrite());
1446 }
1447
1448 // play it safe and append (rather than set) the sender state,
1449 // as forwarded packets may already have existing state
1450 pkt->pushSenderState(mshr);
1451
1452 if (pkt->isClean() && blk && blk->isDirty()) {
1453 // A cache clean opearation is looking for a dirty block. Mark
1454 // the packet so that the destination xbar can determine that
1455 // there will be a follow-up write packet as well.
1456 pkt->setSatisfied();
1457 }
1458
1459 if (!memSidePort.sendTimingReq(pkt)) {
1460 // we are awaiting a retry, but we
1461 // delete the packet and will be creating a new packet
1462 // when we get the opportunity
1463 delete pkt;
1464
1465 // note that we have now masked any requestBus and
1466 // schedSendEvent (we will wait for a retry before
1467 // doing anything), and this is so even if we do not
1468 // care about this packet and might override it before
1469 // it gets retried
1470 return true;
1471 } else {
1472 // As part of the call to sendTimingReq the packet is
1473 // forwarded to all neighbouring caches (and any caches
1474 // above them) as a snoop. Thus at this point we know if
1475 // any of the neighbouring caches are responding, and if
1476 // so, we know it is dirty, and we can determine if it is
1477 // being passed as Modified, making our MSHR the ordering
1478 // point
1479 bool pending_modified_resp = !pkt->hasSharers() &&
1480 pkt->cacheResponding();
1481 markInService(mshr, pending_modified_resp);
1482
1483 if (pkt->isClean() && blk && blk->isDirty()) {
1484 // A cache clean opearation is looking for a dirty
1485 // block. If a dirty block is encountered a WriteClean
1486 // will update any copies to the path to the memory
1487 // until the point of reference.
1488 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
1489 __func__, pkt->print(), blk->print());
1490 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(),
1491 pkt->id);
1492 PacketList writebacks;
1493 writebacks.push_back(wb_pkt);
1494 doWritebacks(writebacks, 0);
1495 }
1496
1497 return false;
1498 }
1499}
1500
1501bool
1502BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
1503{
1504 assert(wq_entry);
1505
1506 // always a single target for write queue entries
1507 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
1508
1509 DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print());
1510
1511 // forward as is, both for evictions and uncacheable writes
1512 if (!memSidePort.sendTimingReq(tgt_pkt)) {
1513 // note that we have now masked any requestBus and
1514 // schedSendEvent (we will wait for a retry before
1515 // doing anything), and this is so even if we do not
1516 // care about this packet and might override it before
1517 // it gets retried
1518 return true;
1519 } else {
1520 markInService(wq_entry);
1521 return false;
1522 }
1523}
1524
1525void
1526BaseCache::serialize(CheckpointOut &cp) const
1527{
1528 bool dirty(isDirty());
1529
1530 if (dirty) {
1531 warn("*** The cache still contains dirty data. ***\n");
1532 warn(" Make sure to drain the system using the correct flags.\n");
1533 warn(" This checkpoint will not restore correctly " \
1534 "and dirty data in the cache will be lost!\n");
1535 }
1536
1537 // Since we don't checkpoint the data in the cache, any dirty data
1538 // will be lost when restoring from a checkpoint of a system that
1539 // wasn't drained properly. Flag the checkpoint as invalid if the
1540 // cache contains dirty data.
1541 bool bad_checkpoint(dirty);
1542 SERIALIZE_SCALAR(bad_checkpoint);
1543}
1544
1545void
1546BaseCache::unserialize(CheckpointIn &cp)
1547{
1548 bool bad_checkpoint;
1549 UNSERIALIZE_SCALAR(bad_checkpoint);
1550 if (bad_checkpoint) {
1551 fatal("Restoring from checkpoints with dirty caches is not "
1552 "supported in the classic memory system. Please remove any "
1553 "caches or drain them properly before taking checkpoints.\n");
1554 }
1555}
1556
1557void
1558BaseCache::regStats()
1559{
1560 MemObject::regStats();
1561
1562 using namespace Stats;
1563
1564 // Hit statistics
1565 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1566 MemCmd cmd(access_idx);
1567 const string &cstr = cmd.toString();
1568
1569 hits[access_idx]
1570 .init(system->maxMasters())
1571 .name(name() + "." + cstr + "_hits")
1572 .desc("number of " + cstr + " hits")
1573 .flags(total | nozero | nonan)
1574 ;
1575 for (int i = 0; i < system->maxMasters(); i++) {
1576 hits[access_idx].subname(i, system->getMasterName(i));
1577 }
1578 }
1579
1580// These macros make it easier to sum the right subset of commands and
1581// to change the subset of commands that are considered "demand" vs
1582// "non-demand"
1583#define SUM_DEMAND(s) \
1584 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
1585 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
1586
1587// should writebacks be included here? prior code was inconsistent...
1588#define SUM_NON_DEMAND(s) \
1589 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1590
1591 demandHits
1592 .name(name() + ".demand_hits")
1593 .desc("number of demand (read+write) hits")
1594 .flags(total | nozero | nonan)
1595 ;
1596 demandHits = SUM_DEMAND(hits);
1597 for (int i = 0; i < system->maxMasters(); i++) {
1598 demandHits.subname(i, system->getMasterName(i));
1599 }
1600
1601 overallHits
1602 .name(name() + ".overall_hits")
1603 .desc("number of overall hits")
1604 .flags(total | nozero | nonan)
1605 ;
1606 overallHits = demandHits + SUM_NON_DEMAND(hits);
1607 for (int i = 0; i < system->maxMasters(); i++) {
1608 overallHits.subname(i, system->getMasterName(i));
1609 }
1610
1611 // Miss statistics
1612 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1613 MemCmd cmd(access_idx);
1614 const string &cstr = cmd.toString();
1615
1616 misses[access_idx]
1617 .init(system->maxMasters())
1618 .name(name() + "." + cstr + "_misses")
1619 .desc("number of " + cstr + " misses")
1620 .flags(total | nozero | nonan)
1621 ;
1622 for (int i = 0; i < system->maxMasters(); i++) {
1623 misses[access_idx].subname(i, system->getMasterName(i));
1624 }
1625 }
1626
1627 demandMisses
1628 .name(name() + ".demand_misses")
1629 .desc("number of demand (read+write) misses")
1630 .flags(total | nozero | nonan)
1631 ;
1632 demandMisses = SUM_DEMAND(misses);
1633 for (int i = 0; i < system->maxMasters(); i++) {
1634 demandMisses.subname(i, system->getMasterName(i));
1635 }
1636
1637 overallMisses
1638 .name(name() + ".overall_misses")
1639 .desc("number of overall misses")
1640 .flags(total | nozero | nonan)
1641 ;
1642 overallMisses = demandMisses + SUM_NON_DEMAND(misses);
1643 for (int i = 0; i < system->maxMasters(); i++) {
1644 overallMisses.subname(i, system->getMasterName(i));
1645 }
1646
1647 // Miss latency statistics
1648 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1649 MemCmd cmd(access_idx);
1650 const string &cstr = cmd.toString();
1651
1652 missLatency[access_idx]
1653 .init(system->maxMasters())
1654 .name(name() + "." + cstr + "_miss_latency")
1655 .desc("number of " + cstr + " miss cycles")
1656 .flags(total | nozero | nonan)
1657 ;
1658 for (int i = 0; i < system->maxMasters(); i++) {
1659 missLatency[access_idx].subname(i, system->getMasterName(i));
1660 }
1661 }
1662
1663 demandMissLatency
1664 .name(name() + ".demand_miss_latency")
1665 .desc("number of demand (read+write) miss cycles")
1666 .flags(total | nozero | nonan)
1667 ;
1668 demandMissLatency = SUM_DEMAND(missLatency);
1669 for (int i = 0; i < system->maxMasters(); i++) {
1670 demandMissLatency.subname(i, system->getMasterName(i));
1671 }
1672
1673 overallMissLatency
1674 .name(name() + ".overall_miss_latency")
1675 .desc("number of overall miss cycles")
1676 .flags(total | nozero | nonan)
1677 ;
1678 overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
1679 for (int i = 0; i < system->maxMasters(); i++) {
1680 overallMissLatency.subname(i, system->getMasterName(i));
1681 }
1682
1683 // access formulas
1684 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1685 MemCmd cmd(access_idx);
1686 const string &cstr = cmd.toString();
1687
1688 accesses[access_idx]
1689 .name(name() + "." + cstr + "_accesses")
1690 .desc("number of " + cstr + " accesses(hits+misses)")
1691 .flags(total | nozero | nonan)
1692 ;
1693 accesses[access_idx] = hits[access_idx] + misses[access_idx];
1694
1695 for (int i = 0; i < system->maxMasters(); i++) {
1696 accesses[access_idx].subname(i, system->getMasterName(i));
1697 }
1698 }
1699
1700 demandAccesses
1701 .name(name() + ".demand_accesses")
1702 .desc("number of demand (read+write) accesses")
1703 .flags(total | nozero | nonan)
1704 ;
1705 demandAccesses = demandHits + demandMisses;
1706 for (int i = 0; i < system->maxMasters(); i++) {
1707 demandAccesses.subname(i, system->getMasterName(i));
1708 }
1709
1710 overallAccesses
1711 .name(name() + ".overall_accesses")
1712 .desc("number of overall (read+write) accesses")
1713 .flags(total | nozero | nonan)
1714 ;
1715 overallAccesses = overallHits + overallMisses;
1716 for (int i = 0; i < system->maxMasters(); i++) {
1717 overallAccesses.subname(i, system->getMasterName(i));
1718 }
1719
1720 // miss rate formulas
1721 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1722 MemCmd cmd(access_idx);
1723 const string &cstr = cmd.toString();
1724
1725 missRate[access_idx]
1726 .name(name() + "." + cstr + "_miss_rate")
1727 .desc("miss rate for " + cstr + " accesses")
1728 .flags(total | nozero | nonan)
1729 ;
1730 missRate[access_idx] = misses[access_idx] / accesses[access_idx];
1731
1732 for (int i = 0; i < system->maxMasters(); i++) {
1733 missRate[access_idx].subname(i, system->getMasterName(i));
1734 }
1735 }
1736
1737 demandMissRate
1738 .name(name() + ".demand_miss_rate")
1739 .desc("miss rate for demand accesses")
1740 .flags(total | nozero | nonan)
1741 ;
1742 demandMissRate = demandMisses / demandAccesses;
1743 for (int i = 0; i < system->maxMasters(); i++) {
1744 demandMissRate.subname(i, system->getMasterName(i));
1745 }
1746
1747 overallMissRate
1748 .name(name() + ".overall_miss_rate")
1749 .desc("miss rate for overall accesses")
1750 .flags(total | nozero | nonan)
1751 ;
1752 overallMissRate = overallMisses / overallAccesses;
1753 for (int i = 0; i < system->maxMasters(); i++) {
1754 overallMissRate.subname(i, system->getMasterName(i));
1755 }
1756
1757 // miss latency formulas
1758 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1759 MemCmd cmd(access_idx);
1760 const string &cstr = cmd.toString();
1761
1762 avgMissLatency[access_idx]
1763 .name(name() + "." + cstr + "_avg_miss_latency")
1764 .desc("average " + cstr + " miss latency")
1765 .flags(total | nozero | nonan)
1766 ;
1767 avgMissLatency[access_idx] =
1768 missLatency[access_idx] / misses[access_idx];
1769
1770 for (int i = 0; i < system->maxMasters(); i++) {
1771 avgMissLatency[access_idx].subname(i, system->getMasterName(i));
1772 }
1773 }
1774
1775 demandAvgMissLatency
1776 .name(name() + ".demand_avg_miss_latency")
1777 .desc("average overall miss latency")
1778 .flags(total | nozero | nonan)
1779 ;
1780 demandAvgMissLatency = demandMissLatency / demandMisses;
1781 for (int i = 0; i < system->maxMasters(); i++) {
1782 demandAvgMissLatency.subname(i, system->getMasterName(i));
1783 }
1784
1785 overallAvgMissLatency
1786 .name(name() + ".overall_avg_miss_latency")
1787 .desc("average overall miss latency")
1788 .flags(total | nozero | nonan)
1789 ;
1790 overallAvgMissLatency = overallMissLatency / overallMisses;
1791 for (int i = 0; i < system->maxMasters(); i++) {
1792 overallAvgMissLatency.subname(i, system->getMasterName(i));
1793 }
1794
1795 blocked_cycles.init(NUM_BLOCKED_CAUSES);
1796 blocked_cycles
1797 .name(name() + ".blocked_cycles")
1798 .desc("number of cycles access was blocked")
1799 .subname(Blocked_NoMSHRs, "no_mshrs")
1800 .subname(Blocked_NoTargets, "no_targets")
1801 ;
1802
1803
1804 blocked_causes.init(NUM_BLOCKED_CAUSES);
1805 blocked_causes
1806 .name(name() + ".blocked")
1807 .desc("number of cycles access was blocked")
1808 .subname(Blocked_NoMSHRs, "no_mshrs")
1809 .subname(Blocked_NoTargets, "no_targets")
1810 ;
1811
1812 avg_blocked
1813 .name(name() + ".avg_blocked_cycles")
1814 .desc("average number of cycles each access was blocked")
1815 .subname(Blocked_NoMSHRs, "no_mshrs")
1816 .subname(Blocked_NoTargets, "no_targets")
1817 ;
1818
1819 avg_blocked = blocked_cycles / blocked_causes;
1820
1821 unusedPrefetches
1822 .name(name() + ".unused_prefetches")
1823 .desc("number of HardPF blocks evicted w/o reference")
1824 .flags(nozero)
1825 ;
1826
1827 writebacks
1828 .init(system->maxMasters())
1829 .name(name() + ".writebacks")
1830 .desc("number of writebacks")
1831 .flags(total | nozero | nonan)
1832 ;
1833 for (int i = 0; i < system->maxMasters(); i++) {
1834 writebacks.subname(i, system->getMasterName(i));
1835 }
1836
1837 // MSHR statistics
1838 // MSHR hit statistics
1839 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1840 MemCmd cmd(access_idx);
1841 const string &cstr = cmd.toString();
1842
1843 mshr_hits[access_idx]
1844 .init(system->maxMasters())
1845 .name(name() + "." + cstr + "_mshr_hits")
1846 .desc("number of " + cstr + " MSHR hits")
1847 .flags(total | nozero | nonan)
1848 ;
1849 for (int i = 0; i < system->maxMasters(); i++) {
1850 mshr_hits[access_idx].subname(i, system->getMasterName(i));
1851 }
1852 }
1853
1854 demandMshrHits
1855 .name(name() + ".demand_mshr_hits")
1856 .desc("number of demand (read+write) MSHR hits")
1857 .flags(total | nozero | nonan)
1858 ;
1859 demandMshrHits = SUM_DEMAND(mshr_hits);
1860 for (int i = 0; i < system->maxMasters(); i++) {
1861 demandMshrHits.subname(i, system->getMasterName(i));
1862 }
1863
1864 overallMshrHits
1865 .name(name() + ".overall_mshr_hits")
1866 .desc("number of overall MSHR hits")
1867 .flags(total | nozero | nonan)
1868 ;
1869 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
1870 for (int i = 0; i < system->maxMasters(); i++) {
1871 overallMshrHits.subname(i, system->getMasterName(i));
1872 }
1873
1874 // MSHR miss statistics
1875 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1876 MemCmd cmd(access_idx);
1877 const string &cstr = cmd.toString();
1878
1879 mshr_misses[access_idx]
1880 .init(system->maxMasters())
1881 .name(name() + "." + cstr + "_mshr_misses")
1882 .desc("number of " + cstr + " MSHR misses")
1883 .flags(total | nozero | nonan)
1884 ;
1885 for (int i = 0; i < system->maxMasters(); i++) {
1886 mshr_misses[access_idx].subname(i, system->getMasterName(i));
1887 }
1888 }
1889
1890 demandMshrMisses
1891 .name(name() + ".demand_mshr_misses")
1892 .desc("number of demand (read+write) MSHR misses")
1893 .flags(total | nozero | nonan)
1894 ;
1895 demandMshrMisses = SUM_DEMAND(mshr_misses);
1896 for (int i = 0; i < system->maxMasters(); i++) {
1897 demandMshrMisses.subname(i, system->getMasterName(i));
1898 }
1899
1900 overallMshrMisses
1901 .name(name() + ".overall_mshr_misses")
1902 .desc("number of overall MSHR misses")
1903 .flags(total | nozero | nonan)
1904 ;
1905 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
1906 for (int i = 0; i < system->maxMasters(); i++) {
1907 overallMshrMisses.subname(i, system->getMasterName(i));
1908 }
1909
1910 // MSHR miss latency statistics
1911 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1912 MemCmd cmd(access_idx);
1913 const string &cstr = cmd.toString();
1914
1915 mshr_miss_latency[access_idx]
1916 .init(system->maxMasters())
1917 .name(name() + "." + cstr + "_mshr_miss_latency")
1918 .desc("number of " + cstr + " MSHR miss cycles")
1919 .flags(total | nozero | nonan)
1920 ;
1921 for (int i = 0; i < system->maxMasters(); i++) {
1922 mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
1923 }
1924 }
1925
1926 demandMshrMissLatency
1927 .name(name() + ".demand_mshr_miss_latency")
1928 .desc("number of demand (read+write) MSHR miss cycles")
1929 .flags(total | nozero | nonan)
1930 ;
1931 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
1932 for (int i = 0; i < system->maxMasters(); i++) {
1933 demandMshrMissLatency.subname(i, system->getMasterName(i));
1934 }
1935
1936 overallMshrMissLatency
1937 .name(name() + ".overall_mshr_miss_latency")
1938 .desc("number of overall MSHR miss cycles")
1939 .flags(total | nozero | nonan)
1940 ;
1941 overallMshrMissLatency =
1942 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
1943 for (int i = 0; i < system->maxMasters(); i++) {
1944 overallMshrMissLatency.subname(i, system->getMasterName(i));
1945 }
1946
1947 // MSHR uncacheable statistics
1948 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1949 MemCmd cmd(access_idx);
1950 const string &cstr = cmd.toString();
1951
1952 mshr_uncacheable[access_idx]
1953 .init(system->maxMasters())
1954 .name(name() + "." + cstr + "_mshr_uncacheable")
1955 .desc("number of " + cstr + " MSHR uncacheable")
1956 .flags(total | nozero | nonan)
1957 ;
1958 for (int i = 0; i < system->maxMasters(); i++) {
1959 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
1960 }
1961 }
1962
1963 overallMshrUncacheable
1964 .name(name() + ".overall_mshr_uncacheable_misses")
1965 .desc("number of overall MSHR uncacheable misses")
1966 .flags(total | nozero | nonan)
1967 ;
1968 overallMshrUncacheable =
1969 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
1970 for (int i = 0; i < system->maxMasters(); i++) {
1971 overallMshrUncacheable.subname(i, system->getMasterName(i));
1972 }
1973
1974 // MSHR miss latency statistics
1975 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1976 MemCmd cmd(access_idx);
1977 const string &cstr = cmd.toString();
1978
1979 mshr_uncacheable_lat[access_idx]
1980 .init(system->maxMasters())
1981 .name(name() + "." + cstr + "_mshr_uncacheable_latency")
1982 .desc("number of " + cstr + " MSHR uncacheable cycles")
1983 .flags(total | nozero | nonan)
1984 ;
1985 for (int i = 0; i < system->maxMasters(); i++) {
1986 mshr_uncacheable_lat[access_idx].subname(
1987 i, system->getMasterName(i));
1988 }
1989 }
1990
1991 overallMshrUncacheableLatency
1992 .name(name() + ".overall_mshr_uncacheable_latency")
1993 .desc("number of overall MSHR uncacheable cycles")
1994 .flags(total | nozero | nonan)
1995 ;
1996 overallMshrUncacheableLatency =
1997 SUM_DEMAND(mshr_uncacheable_lat) +
1998 SUM_NON_DEMAND(mshr_uncacheable_lat);
1999 for (int i = 0; i < system->maxMasters(); i++) {
2000 overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
2001 }
2002
2003#if 0
2004 // MSHR access formulas
2005 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2006 MemCmd cmd(access_idx);
2007 const string &cstr = cmd.toString();
2008
2009 mshrAccesses[access_idx]
2010 .name(name() + "." + cstr + "_mshr_accesses")
2011 .desc("number of " + cstr + " mshr accesses(hits+misses)")
2012 .flags(total | nozero | nonan)
2013 ;
2014 mshrAccesses[access_idx] =
2015 mshr_hits[access_idx] + mshr_misses[access_idx]
2016 + mshr_uncacheable[access_idx];
2017 }
2018
2019 demandMshrAccesses
2020 .name(name() + ".demand_mshr_accesses")
2021 .desc("number of demand (read+write) mshr accesses")
2022 .flags(total | nozero | nonan)
2023 ;
2024 demandMshrAccesses = demandMshrHits + demandMshrMisses;
2025
2026 overallMshrAccesses
2027 .name(name() + ".overall_mshr_accesses")
2028 .desc("number of overall (read+write) mshr accesses")
2029 .flags(total | nozero | nonan)
2030 ;
2031 overallMshrAccesses = overallMshrHits + overallMshrMisses
2032 + overallMshrUncacheable;
2033#endif
2034
2035 // MSHR miss rate formulas
2036 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2037 MemCmd cmd(access_idx);
2038 const string &cstr = cmd.toString();
2039
2040 mshrMissRate[access_idx]
2041 .name(name() + "." + cstr + "_mshr_miss_rate")
2042 .desc("mshr miss rate for " + cstr + " accesses")
2043 .flags(total | nozero | nonan)
2044 ;
2045 mshrMissRate[access_idx] =
2046 mshr_misses[access_idx] / accesses[access_idx];
2047
2048 for (int i = 0; i < system->maxMasters(); i++) {
2049 mshrMissRate[access_idx].subname(i, system->getMasterName(i));
2050 }
2051 }
2052
2053 demandMshrMissRate
2054 .name(name() + ".demand_mshr_miss_rate")
2055 .desc("mshr miss rate for demand accesses")
2056 .flags(total | nozero | nonan)
2057 ;
2058 demandMshrMissRate = demandMshrMisses / demandAccesses;
2059 for (int i = 0; i < system->maxMasters(); i++) {
2060 demandMshrMissRate.subname(i, system->getMasterName(i));
2061 }
2062
2063 overallMshrMissRate
2064 .name(name() + ".overall_mshr_miss_rate")
2065 .desc("mshr miss rate for overall accesses")
2066 .flags(total | nozero | nonan)
2067 ;
2068 overallMshrMissRate = overallMshrMisses / overallAccesses;
2069 for (int i = 0; i < system->maxMasters(); i++) {
2070 overallMshrMissRate.subname(i, system->getMasterName(i));
2071 }
2072
2073 // mshrMiss latency formulas
2074 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2075 MemCmd cmd(access_idx);
2076 const string &cstr = cmd.toString();
2077
2078 avgMshrMissLatency[access_idx]
2079 .name(name() + "." + cstr + "_avg_mshr_miss_latency")
2080 .desc("average " + cstr + " mshr miss latency")
2081 .flags(total | nozero | nonan)
2082 ;
2083 avgMshrMissLatency[access_idx] =
2084 mshr_miss_latency[access_idx] / mshr_misses[access_idx];
2085
2086 for (int i = 0; i < system->maxMasters(); i++) {
2087 avgMshrMissLatency[access_idx].subname(
2088 i, system->getMasterName(i));
2089 }
2090 }
2091
2092 demandAvgMshrMissLatency
2093 .name(name() + ".demand_avg_mshr_miss_latency")
2094 .desc("average overall mshr miss latency")
2095 .flags(total | nozero | nonan)
2096 ;
2097 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
2098 for (int i = 0; i < system->maxMasters(); i++) {
2099 demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
2100 }
2101
2102 overallAvgMshrMissLatency
2103 .name(name() + ".overall_avg_mshr_miss_latency")
2104 .desc("average overall mshr miss latency")
2105 .flags(total | nozero | nonan)
2106 ;
2107 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
2108 for (int i = 0; i < system->maxMasters(); i++) {
2109 overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
2110 }
2111
2112 // mshrUncacheable latency formulas
2113 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2114 MemCmd cmd(access_idx);
2115 const string &cstr = cmd.toString();
2116
2117 avgMshrUncacheableLatency[access_idx]
2118 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
2119 .desc("average " + cstr + " mshr uncacheable latency")
2120 .flags(total | nozero | nonan)
2121 ;
2122 avgMshrUncacheableLatency[access_idx] =
2123 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
2124
2125 for (int i = 0; i < system->maxMasters(); i++) {
2126 avgMshrUncacheableLatency[access_idx].subname(
2127 i, system->getMasterName(i));
2128 }
2129 }
2130
2131 overallAvgMshrUncacheableLatency
2132 .name(name() + ".overall_avg_mshr_uncacheable_latency")
2133 .desc("average overall mshr uncacheable latency")
2134 .flags(total | nozero | nonan)
2135 ;
2136 overallAvgMshrUncacheableLatency =
2137 overallMshrUncacheableLatency / overallMshrUncacheable;
2138 for (int i = 0; i < system->maxMasters(); i++) {
2139 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
2140 }
2141
2142 replacements
2143 .name(name() + ".replacements")
2144 .desc("number of replacements")
2145 ;
2146}
2147
2148///////////////
2149//
2150// CpuSidePort
2151//
2152///////////////
2153bool
2154BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2155{
2156 // Snoops shouldn't happen when bypassing caches
2157 assert(!cache->system->bypassCaches());
2158
2159 assert(pkt->isResponse());
2160
2161 // Express snoop responses from master to slave, e.g., from L1 to L2
2162 cache->recvTimingSnoopResp(pkt);
2163 return true;
2164}
2165
2166
2167bool
2168BaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
2169{
2170 if (cache->system->bypassCaches() || pkt->isExpressSnoop()) {
2171 // always let express snoop packets through even if blocked
2172 return true;
2173 } else if (blocked || mustSendRetry) {
2174 // either already committed to send a retry, or blocked
2175 mustSendRetry = true;
2176 return false;
2177 }
2178 mustSendRetry = false;
2179 return true;
2180}
2181
2182bool
2183BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2184{
2185 assert(pkt->isRequest());
2186
2187 if (cache->system->bypassCaches()) {
2188 // Just forward the packet if caches are disabled.
2189 // @todo This should really enqueue the packet rather
2190 bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt);
2191 assert(success);
2192 return true;
2193 } else if (tryTiming(pkt)) {
2194 cache->recvTimingReq(pkt);
2195 return true;
2196 }
2197 return false;
2198}
2199
2200Tick
2201BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
2202{
2203 if (cache->system->bypassCaches()) {
2204 // Forward the request if the system is in cache bypass mode.
2205 return cache->memSidePort.sendAtomic(pkt);
2206 } else {
2207 return cache->recvAtomic(pkt);
2208 }
2209}
2210
2211void
2212BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
2213{
2214 if (cache->system->bypassCaches()) {
2215 // The cache should be flushed if we are in cache bypass mode,
2216 // so we don't need to check if we need to update anything.
2217 cache->memSidePort.sendFunctional(pkt);
2218 return;
2219 }
2220
2221 // functional request
2222 cache->functionalAccess(pkt, true);
2223}
2224
2225AddrRangeList
2226BaseCache::CpuSidePort::getAddrRanges() const
2227{
2228 return cache->getAddrRanges();
2229}
2230
2231
2232BaseCache::
2233CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache,
2234 const std::string &_label)
2235 : CacheSlavePort(_name, _cache, _label), cache(_cache)
2236{
2237}
2238
2239///////////////
2240//
2241// MemSidePort
2242//
2243///////////////
2244bool
2245BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt)
2246{
2247 cache->recvTimingResp(pkt);
2248 return true;
2249}
2250
2251// Express snooping requests to memside port
2252void
2253BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2254{
2255 // Snoops shouldn't happen when bypassing caches
2256 assert(!cache->system->bypassCaches());
2257
2258 // handle snooping requests
2259 cache->recvTimingSnoopReq(pkt);
2260}
2261
2262Tick
2263BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2264{
2265 // Snoops shouldn't happen when bypassing caches
2266 assert(!cache->system->bypassCaches());
2267
2268 return cache->recvAtomicSnoop(pkt);
2269}
2270
2271void
2272BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2273{
2274 // Snoops shouldn't happen when bypassing caches
2275 assert(!cache->system->bypassCaches());
2276
2277 // functional snoop (note that in contrast to atomic we don't have
2278 // a specific functionalSnoop method, as they have the same
2279 // behaviour regardless)
2280 cache->functionalAccess(pkt, false);
2281}
2282
2283void
2284BaseCache::CacheReqPacketQueue::sendDeferredPacket()
2285{
2286 // sanity check
2287 assert(!waitingOnRetry);
2288
2289 // there should never be any deferred request packets in the
2290 // queue, instead we resly on the cache to provide the packets
2291 // from the MSHR queue or write queue
2292 assert(deferredPacketReadyTime() == MaxTick);
2293
2294 // check for request packets (requests & writebacks)
2295 QueueEntry* entry = cache.getNextQueueEntry();
2296
2297 if (!entry) {
2298 // can happen if e.g. we attempt a writeback and fail, but
2299 // before the retry, the writeback is eliminated because
2300 // we snoop another cache's ReadEx.
2301 } else {
2302 // let our snoop responses go first if there are responses to
2303 // the same addresses
2304 if (checkConflictingSnoop(entry->blkAddr)) {
2305 return;
2306 }
2307 waitingOnRetry = entry->sendPacket(cache);
2308 }
2309
2310 // if we succeeded and are not waiting for a retry, schedule the
2311 // next send considering when the next queue is ready, note that
2312 // snoop responses have their own packet queue and thus schedule
2313 // their own events
2314 if (!waitingOnRetry) {
2315 schedSendEvent(cache.nextQueueReadyTime());
2316 }
2317}
2318
2319BaseCache::MemSidePort::MemSidePort(const std::string &_name,
2320 BaseCache *_cache,
2321 const std::string &_label)
2322 : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2323 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2324 _snoopRespQueue(*_cache, *this, _label), cache(_cache)
2325{
2326}
| 1386 packet.dataStatic(blk.data);
1387
1388 memSidePort.sendFunctional(&packet);
1389
1390 blk.status &= ~BlkDirty;
1391 }
1392}
1393
1394void
1395BaseCache::invalidateVisitor(CacheBlk &blk)
1396{
1397 if (blk.isDirty())
1398 warn_once("Invalidating dirty cache lines. " \
1399 "Expect things to break.\n");
1400
1401 if (blk.isValid()) {
1402 assert(!blk.isDirty());
1403 invalidateBlock(&blk);
1404 }
1405}
1406
1407Tick
1408BaseCache::nextQueueReadyTime() const
1409{
1410 Tick nextReady = std::min(mshrQueue.nextReadyTime(),
1411 writeBuffer.nextReadyTime());
1412
1413 // Don't signal prefetch ready time if no MSHRs available
1414 // Will signal once enoguh MSHRs are deallocated
1415 if (prefetcher && mshrQueue.canPrefetch()) {
1416 nextReady = std::min(nextReady,
1417 prefetcher->nextPrefetchReadyTime());
1418 }
1419
1420 return nextReady;
1421}
1422
1423
1424bool
1425BaseCache::sendMSHRQueuePacket(MSHR* mshr)
1426{
1427 assert(mshr);
1428
1429 // use request from 1st target
1430 PacketPtr tgt_pkt = mshr->getTarget()->pkt;
1431
1432 DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print());
1433
1434 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
1435
1436 // either a prefetch that is not present upstream, or a normal
1437 // MSHR request, proceed to get the packet to send downstream
1438 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
1439
1440 mshr->isForward = (pkt == nullptr);
1441
1442 if (mshr->isForward) {
1443 // not a cache block request, but a response is expected
1444 // make copy of current packet to forward, keep current
1445 // copy for response handling
1446 pkt = new Packet(tgt_pkt, false, true);
1447 assert(!pkt->isWrite());
1448 }
1449
1450 // play it safe and append (rather than set) the sender state,
1451 // as forwarded packets may already have existing state
1452 pkt->pushSenderState(mshr);
1453
1454 if (pkt->isClean() && blk && blk->isDirty()) {
1455 // A cache clean opearation is looking for a dirty block. Mark
1456 // the packet so that the destination xbar can determine that
1457 // there will be a follow-up write packet as well.
1458 pkt->setSatisfied();
1459 }
1460
1461 if (!memSidePort.sendTimingReq(pkt)) {
1462 // we are awaiting a retry, but we
1463 // delete the packet and will be creating a new packet
1464 // when we get the opportunity
1465 delete pkt;
1466
1467 // note that we have now masked any requestBus and
1468 // schedSendEvent (we will wait for a retry before
1469 // doing anything), and this is so even if we do not
1470 // care about this packet and might override it before
1471 // it gets retried
1472 return true;
1473 } else {
1474 // As part of the call to sendTimingReq the packet is
1475 // forwarded to all neighbouring caches (and any caches
1476 // above them) as a snoop. Thus at this point we know if
1477 // any of the neighbouring caches are responding, and if
1478 // so, we know it is dirty, and we can determine if it is
1479 // being passed as Modified, making our MSHR the ordering
1480 // point
1481 bool pending_modified_resp = !pkt->hasSharers() &&
1482 pkt->cacheResponding();
1483 markInService(mshr, pending_modified_resp);
1484
1485 if (pkt->isClean() && blk && blk->isDirty()) {
1486 // A cache clean opearation is looking for a dirty
1487 // block. If a dirty block is encountered a WriteClean
1488 // will update any copies to the path to the memory
1489 // until the point of reference.
1490 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
1491 __func__, pkt->print(), blk->print());
1492 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(),
1493 pkt->id);
1494 PacketList writebacks;
1495 writebacks.push_back(wb_pkt);
1496 doWritebacks(writebacks, 0);
1497 }
1498
1499 return false;
1500 }
1501}
1502
1503bool
1504BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
1505{
1506 assert(wq_entry);
1507
1508 // always a single target for write queue entries
1509 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
1510
1511 DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print());
1512
1513 // forward as is, both for evictions and uncacheable writes
1514 if (!memSidePort.sendTimingReq(tgt_pkt)) {
1515 // note that we have now masked any requestBus and
1516 // schedSendEvent (we will wait for a retry before
1517 // doing anything), and this is so even if we do not
1518 // care about this packet and might override it before
1519 // it gets retried
1520 return true;
1521 } else {
1522 markInService(wq_entry);
1523 return false;
1524 }
1525}
1526
1527void
1528BaseCache::serialize(CheckpointOut &cp) const
1529{
1530 bool dirty(isDirty());
1531
1532 if (dirty) {
1533 warn("*** The cache still contains dirty data. ***\n");
1534 warn(" Make sure to drain the system using the correct flags.\n");
1535 warn(" This checkpoint will not restore correctly " \
1536 "and dirty data in the cache will be lost!\n");
1537 }
1538
1539 // Since we don't checkpoint the data in the cache, any dirty data
1540 // will be lost when restoring from a checkpoint of a system that
1541 // wasn't drained properly. Flag the checkpoint as invalid if the
1542 // cache contains dirty data.
1543 bool bad_checkpoint(dirty);
1544 SERIALIZE_SCALAR(bad_checkpoint);
1545}
1546
1547void
1548BaseCache::unserialize(CheckpointIn &cp)
1549{
1550 bool bad_checkpoint;
1551 UNSERIALIZE_SCALAR(bad_checkpoint);
1552 if (bad_checkpoint) {
1553 fatal("Restoring from checkpoints with dirty caches is not "
1554 "supported in the classic memory system. Please remove any "
1555 "caches or drain them properly before taking checkpoints.\n");
1556 }
1557}
1558
1559void
1560BaseCache::regStats()
1561{
1562 MemObject::regStats();
1563
1564 using namespace Stats;
1565
1566 // Hit statistics
1567 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1568 MemCmd cmd(access_idx);
1569 const string &cstr = cmd.toString();
1570
1571 hits[access_idx]
1572 .init(system->maxMasters())
1573 .name(name() + "." + cstr + "_hits")
1574 .desc("number of " + cstr + " hits")
1575 .flags(total | nozero | nonan)
1576 ;
1577 for (int i = 0; i < system->maxMasters(); i++) {
1578 hits[access_idx].subname(i, system->getMasterName(i));
1579 }
1580 }
1581
1582// These macros make it easier to sum the right subset of commands and
1583// to change the subset of commands that are considered "demand" vs
1584// "non-demand"
1585#define SUM_DEMAND(s) \
1586 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
1587 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
1588
1589// should writebacks be included here? prior code was inconsistent...
1590#define SUM_NON_DEMAND(s) \
1591 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1592
1593 demandHits
1594 .name(name() + ".demand_hits")
1595 .desc("number of demand (read+write) hits")
1596 .flags(total | nozero | nonan)
1597 ;
1598 demandHits = SUM_DEMAND(hits);
1599 for (int i = 0; i < system->maxMasters(); i++) {
1600 demandHits.subname(i, system->getMasterName(i));
1601 }
1602
1603 overallHits
1604 .name(name() + ".overall_hits")
1605 .desc("number of overall hits")
1606 .flags(total | nozero | nonan)
1607 ;
1608 overallHits = demandHits + SUM_NON_DEMAND(hits);
1609 for (int i = 0; i < system->maxMasters(); i++) {
1610 overallHits.subname(i, system->getMasterName(i));
1611 }
1612
1613 // Miss statistics
1614 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1615 MemCmd cmd(access_idx);
1616 const string &cstr = cmd.toString();
1617
1618 misses[access_idx]
1619 .init(system->maxMasters())
1620 .name(name() + "." + cstr + "_misses")
1621 .desc("number of " + cstr + " misses")
1622 .flags(total | nozero | nonan)
1623 ;
1624 for (int i = 0; i < system->maxMasters(); i++) {
1625 misses[access_idx].subname(i, system->getMasterName(i));
1626 }
1627 }
1628
1629 demandMisses
1630 .name(name() + ".demand_misses")
1631 .desc("number of demand (read+write) misses")
1632 .flags(total | nozero | nonan)
1633 ;
1634 demandMisses = SUM_DEMAND(misses);
1635 for (int i = 0; i < system->maxMasters(); i++) {
1636 demandMisses.subname(i, system->getMasterName(i));
1637 }
1638
1639 overallMisses
1640 .name(name() + ".overall_misses")
1641 .desc("number of overall misses")
1642 .flags(total | nozero | nonan)
1643 ;
1644 overallMisses = demandMisses + SUM_NON_DEMAND(misses);
1645 for (int i = 0; i < system->maxMasters(); i++) {
1646 overallMisses.subname(i, system->getMasterName(i));
1647 }
1648
1649 // Miss latency statistics
1650 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1651 MemCmd cmd(access_idx);
1652 const string &cstr = cmd.toString();
1653
1654 missLatency[access_idx]
1655 .init(system->maxMasters())
1656 .name(name() + "." + cstr + "_miss_latency")
1657 .desc("number of " + cstr + " miss cycles")
1658 .flags(total | nozero | nonan)
1659 ;
1660 for (int i = 0; i < system->maxMasters(); i++) {
1661 missLatency[access_idx].subname(i, system->getMasterName(i));
1662 }
1663 }
1664
1665 demandMissLatency
1666 .name(name() + ".demand_miss_latency")
1667 .desc("number of demand (read+write) miss cycles")
1668 .flags(total | nozero | nonan)
1669 ;
1670 demandMissLatency = SUM_DEMAND(missLatency);
1671 for (int i = 0; i < system->maxMasters(); i++) {
1672 demandMissLatency.subname(i, system->getMasterName(i));
1673 }
1674
1675 overallMissLatency
1676 .name(name() + ".overall_miss_latency")
1677 .desc("number of overall miss cycles")
1678 .flags(total | nozero | nonan)
1679 ;
1680 overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
1681 for (int i = 0; i < system->maxMasters(); i++) {
1682 overallMissLatency.subname(i, system->getMasterName(i));
1683 }
1684
1685 // access formulas
1686 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1687 MemCmd cmd(access_idx);
1688 const string &cstr = cmd.toString();
1689
1690 accesses[access_idx]
1691 .name(name() + "." + cstr + "_accesses")
1692 .desc("number of " + cstr + " accesses(hits+misses)")
1693 .flags(total | nozero | nonan)
1694 ;
1695 accesses[access_idx] = hits[access_idx] + misses[access_idx];
1696
1697 for (int i = 0; i < system->maxMasters(); i++) {
1698 accesses[access_idx].subname(i, system->getMasterName(i));
1699 }
1700 }
1701
1702 demandAccesses
1703 .name(name() + ".demand_accesses")
1704 .desc("number of demand (read+write) accesses")
1705 .flags(total | nozero | nonan)
1706 ;
1707 demandAccesses = demandHits + demandMisses;
1708 for (int i = 0; i < system->maxMasters(); i++) {
1709 demandAccesses.subname(i, system->getMasterName(i));
1710 }
1711
1712 overallAccesses
1713 .name(name() + ".overall_accesses")
1714 .desc("number of overall (read+write) accesses")
1715 .flags(total | nozero | nonan)
1716 ;
1717 overallAccesses = overallHits + overallMisses;
1718 for (int i = 0; i < system->maxMasters(); i++) {
1719 overallAccesses.subname(i, system->getMasterName(i));
1720 }
1721
1722 // miss rate formulas
1723 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1724 MemCmd cmd(access_idx);
1725 const string &cstr = cmd.toString();
1726
1727 missRate[access_idx]
1728 .name(name() + "." + cstr + "_miss_rate")
1729 .desc("miss rate for " + cstr + " accesses")
1730 .flags(total | nozero | nonan)
1731 ;
1732 missRate[access_idx] = misses[access_idx] / accesses[access_idx];
1733
1734 for (int i = 0; i < system->maxMasters(); i++) {
1735 missRate[access_idx].subname(i, system->getMasterName(i));
1736 }
1737 }
1738
1739 demandMissRate
1740 .name(name() + ".demand_miss_rate")
1741 .desc("miss rate for demand accesses")
1742 .flags(total | nozero | nonan)
1743 ;
1744 demandMissRate = demandMisses / demandAccesses;
1745 for (int i = 0; i < system->maxMasters(); i++) {
1746 demandMissRate.subname(i, system->getMasterName(i));
1747 }
1748
1749 overallMissRate
1750 .name(name() + ".overall_miss_rate")
1751 .desc("miss rate for overall accesses")
1752 .flags(total | nozero | nonan)
1753 ;
1754 overallMissRate = overallMisses / overallAccesses;
1755 for (int i = 0; i < system->maxMasters(); i++) {
1756 overallMissRate.subname(i, system->getMasterName(i));
1757 }
1758
1759 // miss latency formulas
1760 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1761 MemCmd cmd(access_idx);
1762 const string &cstr = cmd.toString();
1763
1764 avgMissLatency[access_idx]
1765 .name(name() + "." + cstr + "_avg_miss_latency")
1766 .desc("average " + cstr + " miss latency")
1767 .flags(total | nozero | nonan)
1768 ;
1769 avgMissLatency[access_idx] =
1770 missLatency[access_idx] / misses[access_idx];
1771
1772 for (int i = 0; i < system->maxMasters(); i++) {
1773 avgMissLatency[access_idx].subname(i, system->getMasterName(i));
1774 }
1775 }
1776
1777 demandAvgMissLatency
1778 .name(name() + ".demand_avg_miss_latency")
1779 .desc("average overall miss latency")
1780 .flags(total | nozero | nonan)
1781 ;
1782 demandAvgMissLatency = demandMissLatency / demandMisses;
1783 for (int i = 0; i < system->maxMasters(); i++) {
1784 demandAvgMissLatency.subname(i, system->getMasterName(i));
1785 }
1786
1787 overallAvgMissLatency
1788 .name(name() + ".overall_avg_miss_latency")
1789 .desc("average overall miss latency")
1790 .flags(total | nozero | nonan)
1791 ;
1792 overallAvgMissLatency = overallMissLatency / overallMisses;
1793 for (int i = 0; i < system->maxMasters(); i++) {
1794 overallAvgMissLatency.subname(i, system->getMasterName(i));
1795 }
1796
1797 blocked_cycles.init(NUM_BLOCKED_CAUSES);
1798 blocked_cycles
1799 .name(name() + ".blocked_cycles")
1800 .desc("number of cycles access was blocked")
1801 .subname(Blocked_NoMSHRs, "no_mshrs")
1802 .subname(Blocked_NoTargets, "no_targets")
1803 ;
1804
1805
1806 blocked_causes.init(NUM_BLOCKED_CAUSES);
1807 blocked_causes
1808 .name(name() + ".blocked")
1809 .desc("number of cycles access was blocked")
1810 .subname(Blocked_NoMSHRs, "no_mshrs")
1811 .subname(Blocked_NoTargets, "no_targets")
1812 ;
1813
1814 avg_blocked
1815 .name(name() + ".avg_blocked_cycles")
1816 .desc("average number of cycles each access was blocked")
1817 .subname(Blocked_NoMSHRs, "no_mshrs")
1818 .subname(Blocked_NoTargets, "no_targets")
1819 ;
1820
1821 avg_blocked = blocked_cycles / blocked_causes;
1822
1823 unusedPrefetches
1824 .name(name() + ".unused_prefetches")
1825 .desc("number of HardPF blocks evicted w/o reference")
1826 .flags(nozero)
1827 ;
1828
1829 writebacks
1830 .init(system->maxMasters())
1831 .name(name() + ".writebacks")
1832 .desc("number of writebacks")
1833 .flags(total | nozero | nonan)
1834 ;
1835 for (int i = 0; i < system->maxMasters(); i++) {
1836 writebacks.subname(i, system->getMasterName(i));
1837 }
1838
1839 // MSHR statistics
1840 // MSHR hit statistics
1841 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1842 MemCmd cmd(access_idx);
1843 const string &cstr = cmd.toString();
1844
1845 mshr_hits[access_idx]
1846 .init(system->maxMasters())
1847 .name(name() + "." + cstr + "_mshr_hits")
1848 .desc("number of " + cstr + " MSHR hits")
1849 .flags(total | nozero | nonan)
1850 ;
1851 for (int i = 0; i < system->maxMasters(); i++) {
1852 mshr_hits[access_idx].subname(i, system->getMasterName(i));
1853 }
1854 }
1855
1856 demandMshrHits
1857 .name(name() + ".demand_mshr_hits")
1858 .desc("number of demand (read+write) MSHR hits")
1859 .flags(total | nozero | nonan)
1860 ;
1861 demandMshrHits = SUM_DEMAND(mshr_hits);
1862 for (int i = 0; i < system->maxMasters(); i++) {
1863 demandMshrHits.subname(i, system->getMasterName(i));
1864 }
1865
1866 overallMshrHits
1867 .name(name() + ".overall_mshr_hits")
1868 .desc("number of overall MSHR hits")
1869 .flags(total | nozero | nonan)
1870 ;
1871 overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
1872 for (int i = 0; i < system->maxMasters(); i++) {
1873 overallMshrHits.subname(i, system->getMasterName(i));
1874 }
1875
1876 // MSHR miss statistics
1877 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1878 MemCmd cmd(access_idx);
1879 const string &cstr = cmd.toString();
1880
1881 mshr_misses[access_idx]
1882 .init(system->maxMasters())
1883 .name(name() + "." + cstr + "_mshr_misses")
1884 .desc("number of " + cstr + " MSHR misses")
1885 .flags(total | nozero | nonan)
1886 ;
1887 for (int i = 0; i < system->maxMasters(); i++) {
1888 mshr_misses[access_idx].subname(i, system->getMasterName(i));
1889 }
1890 }
1891
1892 demandMshrMisses
1893 .name(name() + ".demand_mshr_misses")
1894 .desc("number of demand (read+write) MSHR misses")
1895 .flags(total | nozero | nonan)
1896 ;
1897 demandMshrMisses = SUM_DEMAND(mshr_misses);
1898 for (int i = 0; i < system->maxMasters(); i++) {
1899 demandMshrMisses.subname(i, system->getMasterName(i));
1900 }
1901
1902 overallMshrMisses
1903 .name(name() + ".overall_mshr_misses")
1904 .desc("number of overall MSHR misses")
1905 .flags(total | nozero | nonan)
1906 ;
1907 overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
1908 for (int i = 0; i < system->maxMasters(); i++) {
1909 overallMshrMisses.subname(i, system->getMasterName(i));
1910 }
1911
1912 // MSHR miss latency statistics
1913 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1914 MemCmd cmd(access_idx);
1915 const string &cstr = cmd.toString();
1916
1917 mshr_miss_latency[access_idx]
1918 .init(system->maxMasters())
1919 .name(name() + "." + cstr + "_mshr_miss_latency")
1920 .desc("number of " + cstr + " MSHR miss cycles")
1921 .flags(total | nozero | nonan)
1922 ;
1923 for (int i = 0; i < system->maxMasters(); i++) {
1924 mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
1925 }
1926 }
1927
1928 demandMshrMissLatency
1929 .name(name() + ".demand_mshr_miss_latency")
1930 .desc("number of demand (read+write) MSHR miss cycles")
1931 .flags(total | nozero | nonan)
1932 ;
1933 demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
1934 for (int i = 0; i < system->maxMasters(); i++) {
1935 demandMshrMissLatency.subname(i, system->getMasterName(i));
1936 }
1937
1938 overallMshrMissLatency
1939 .name(name() + ".overall_mshr_miss_latency")
1940 .desc("number of overall MSHR miss cycles")
1941 .flags(total | nozero | nonan)
1942 ;
1943 overallMshrMissLatency =
1944 demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
1945 for (int i = 0; i < system->maxMasters(); i++) {
1946 overallMshrMissLatency.subname(i, system->getMasterName(i));
1947 }
1948
1949 // MSHR uncacheable statistics
1950 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1951 MemCmd cmd(access_idx);
1952 const string &cstr = cmd.toString();
1953
1954 mshr_uncacheable[access_idx]
1955 .init(system->maxMasters())
1956 .name(name() + "." + cstr + "_mshr_uncacheable")
1957 .desc("number of " + cstr + " MSHR uncacheable")
1958 .flags(total | nozero | nonan)
1959 ;
1960 for (int i = 0; i < system->maxMasters(); i++) {
1961 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
1962 }
1963 }
1964
1965 overallMshrUncacheable
1966 .name(name() + ".overall_mshr_uncacheable_misses")
1967 .desc("number of overall MSHR uncacheable misses")
1968 .flags(total | nozero | nonan)
1969 ;
1970 overallMshrUncacheable =
1971 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
1972 for (int i = 0; i < system->maxMasters(); i++) {
1973 overallMshrUncacheable.subname(i, system->getMasterName(i));
1974 }
1975
1976 // MSHR miss latency statistics
1977 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1978 MemCmd cmd(access_idx);
1979 const string &cstr = cmd.toString();
1980
1981 mshr_uncacheable_lat[access_idx]
1982 .init(system->maxMasters())
1983 .name(name() + "." + cstr + "_mshr_uncacheable_latency")
1984 .desc("number of " + cstr + " MSHR uncacheable cycles")
1985 .flags(total | nozero | nonan)
1986 ;
1987 for (int i = 0; i < system->maxMasters(); i++) {
1988 mshr_uncacheable_lat[access_idx].subname(
1989 i, system->getMasterName(i));
1990 }
1991 }
1992
1993 overallMshrUncacheableLatency
1994 .name(name() + ".overall_mshr_uncacheable_latency")
1995 .desc("number of overall MSHR uncacheable cycles")
1996 .flags(total | nozero | nonan)
1997 ;
1998 overallMshrUncacheableLatency =
1999 SUM_DEMAND(mshr_uncacheable_lat) +
2000 SUM_NON_DEMAND(mshr_uncacheable_lat);
2001 for (int i = 0; i < system->maxMasters(); i++) {
2002 overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
2003 }
2004
2005#if 0
2006 // MSHR access formulas
2007 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2008 MemCmd cmd(access_idx);
2009 const string &cstr = cmd.toString();
2010
2011 mshrAccesses[access_idx]
2012 .name(name() + "." + cstr + "_mshr_accesses")
2013 .desc("number of " + cstr + " mshr accesses(hits+misses)")
2014 .flags(total | nozero | nonan)
2015 ;
2016 mshrAccesses[access_idx] =
2017 mshr_hits[access_idx] + mshr_misses[access_idx]
2018 + mshr_uncacheable[access_idx];
2019 }
2020
2021 demandMshrAccesses
2022 .name(name() + ".demand_mshr_accesses")
2023 .desc("number of demand (read+write) mshr accesses")
2024 .flags(total | nozero | nonan)
2025 ;
2026 demandMshrAccesses = demandMshrHits + demandMshrMisses;
2027
2028 overallMshrAccesses
2029 .name(name() + ".overall_mshr_accesses")
2030 .desc("number of overall (read+write) mshr accesses")
2031 .flags(total | nozero | nonan)
2032 ;
2033 overallMshrAccesses = overallMshrHits + overallMshrMisses
2034 + overallMshrUncacheable;
2035#endif
2036
2037 // MSHR miss rate formulas
2038 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2039 MemCmd cmd(access_idx);
2040 const string &cstr = cmd.toString();
2041
2042 mshrMissRate[access_idx]
2043 .name(name() + "." + cstr + "_mshr_miss_rate")
2044 .desc("mshr miss rate for " + cstr + " accesses")
2045 .flags(total | nozero | nonan)
2046 ;
2047 mshrMissRate[access_idx] =
2048 mshr_misses[access_idx] / accesses[access_idx];
2049
2050 for (int i = 0; i < system->maxMasters(); i++) {
2051 mshrMissRate[access_idx].subname(i, system->getMasterName(i));
2052 }
2053 }
2054
2055 demandMshrMissRate
2056 .name(name() + ".demand_mshr_miss_rate")
2057 .desc("mshr miss rate for demand accesses")
2058 .flags(total | nozero | nonan)
2059 ;
2060 demandMshrMissRate = demandMshrMisses / demandAccesses;
2061 for (int i = 0; i < system->maxMasters(); i++) {
2062 demandMshrMissRate.subname(i, system->getMasterName(i));
2063 }
2064
2065 overallMshrMissRate
2066 .name(name() + ".overall_mshr_miss_rate")
2067 .desc("mshr miss rate for overall accesses")
2068 .flags(total | nozero | nonan)
2069 ;
2070 overallMshrMissRate = overallMshrMisses / overallAccesses;
2071 for (int i = 0; i < system->maxMasters(); i++) {
2072 overallMshrMissRate.subname(i, system->getMasterName(i));
2073 }
2074
2075 // mshrMiss latency formulas
2076 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2077 MemCmd cmd(access_idx);
2078 const string &cstr = cmd.toString();
2079
2080 avgMshrMissLatency[access_idx]
2081 .name(name() + "." + cstr + "_avg_mshr_miss_latency")
2082 .desc("average " + cstr + " mshr miss latency")
2083 .flags(total | nozero | nonan)
2084 ;
2085 avgMshrMissLatency[access_idx] =
2086 mshr_miss_latency[access_idx] / mshr_misses[access_idx];
2087
2088 for (int i = 0; i < system->maxMasters(); i++) {
2089 avgMshrMissLatency[access_idx].subname(
2090 i, system->getMasterName(i));
2091 }
2092 }
2093
2094 demandAvgMshrMissLatency
2095 .name(name() + ".demand_avg_mshr_miss_latency")
2096 .desc("average overall mshr miss latency")
2097 .flags(total | nozero | nonan)
2098 ;
2099 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
2100 for (int i = 0; i < system->maxMasters(); i++) {
2101 demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
2102 }
2103
2104 overallAvgMshrMissLatency
2105 .name(name() + ".overall_avg_mshr_miss_latency")
2106 .desc("average overall mshr miss latency")
2107 .flags(total | nozero | nonan)
2108 ;
2109 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
2110 for (int i = 0; i < system->maxMasters(); i++) {
2111 overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
2112 }
2113
2114 // mshrUncacheable latency formulas
2115 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2116 MemCmd cmd(access_idx);
2117 const string &cstr = cmd.toString();
2118
2119 avgMshrUncacheableLatency[access_idx]
2120 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
2121 .desc("average " + cstr + " mshr uncacheable latency")
2122 .flags(total | nozero | nonan)
2123 ;
2124 avgMshrUncacheableLatency[access_idx] =
2125 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
2126
2127 for (int i = 0; i < system->maxMasters(); i++) {
2128 avgMshrUncacheableLatency[access_idx].subname(
2129 i, system->getMasterName(i));
2130 }
2131 }
2132
2133 overallAvgMshrUncacheableLatency
2134 .name(name() + ".overall_avg_mshr_uncacheable_latency")
2135 .desc("average overall mshr uncacheable latency")
2136 .flags(total | nozero | nonan)
2137 ;
2138 overallAvgMshrUncacheableLatency =
2139 overallMshrUncacheableLatency / overallMshrUncacheable;
2140 for (int i = 0; i < system->maxMasters(); i++) {
2141 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
2142 }
2143
2144 replacements
2145 .name(name() + ".replacements")
2146 .desc("number of replacements")
2147 ;
2148}
2149
2150///////////////
2151//
2152// CpuSidePort
2153//
2154///////////////
2155bool
2156BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2157{
2158 // Snoops shouldn't happen when bypassing caches
2159 assert(!cache->system->bypassCaches());
2160
2161 assert(pkt->isResponse());
2162
2163 // Express snoop responses from master to slave, e.g., from L1 to L2
2164 cache->recvTimingSnoopResp(pkt);
2165 return true;
2166}
2167
2168
2169bool
2170BaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
2171{
2172 if (cache->system->bypassCaches() || pkt->isExpressSnoop()) {
2173 // always let express snoop packets through even if blocked
2174 return true;
2175 } else if (blocked || mustSendRetry) {
2176 // either already committed to send a retry, or blocked
2177 mustSendRetry = true;
2178 return false;
2179 }
2180 mustSendRetry = false;
2181 return true;
2182}
2183
2184bool
2185BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2186{
2187 assert(pkt->isRequest());
2188
2189 if (cache->system->bypassCaches()) {
2190 // Just forward the packet if caches are disabled.
2191 // @todo This should really enqueue the packet rather
2192 bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt);
2193 assert(success);
2194 return true;
2195 } else if (tryTiming(pkt)) {
2196 cache->recvTimingReq(pkt);
2197 return true;
2198 }
2199 return false;
2200}
2201
2202Tick
2203BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
2204{
2205 if (cache->system->bypassCaches()) {
2206 // Forward the request if the system is in cache bypass mode.
2207 return cache->memSidePort.sendAtomic(pkt);
2208 } else {
2209 return cache->recvAtomic(pkt);
2210 }
2211}
2212
2213void
2214BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
2215{
2216 if (cache->system->bypassCaches()) {
2217 // The cache should be flushed if we are in cache bypass mode,
2218 // so we don't need to check if we need to update anything.
2219 cache->memSidePort.sendFunctional(pkt);
2220 return;
2221 }
2222
2223 // functional request
2224 cache->functionalAccess(pkt, true);
2225}
2226
2227AddrRangeList
2228BaseCache::CpuSidePort::getAddrRanges() const
2229{
2230 return cache->getAddrRanges();
2231}
2232
2233
2234BaseCache::
2235CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache,
2236 const std::string &_label)
2237 : CacheSlavePort(_name, _cache, _label), cache(_cache)
2238{
2239}
2240
2241///////////////
2242//
2243// MemSidePort
2244//
2245///////////////
2246bool
2247BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt)
2248{
2249 cache->recvTimingResp(pkt);
2250 return true;
2251}
2252
2253// Express snooping requests to memside port
2254void
2255BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2256{
2257 // Snoops shouldn't happen when bypassing caches
2258 assert(!cache->system->bypassCaches());
2259
2260 // handle snooping requests
2261 cache->recvTimingSnoopReq(pkt);
2262}
2263
2264Tick
2265BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2266{
2267 // Snoops shouldn't happen when bypassing caches
2268 assert(!cache->system->bypassCaches());
2269
2270 return cache->recvAtomicSnoop(pkt);
2271}
2272
2273void
2274BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2275{
2276 // Snoops shouldn't happen when bypassing caches
2277 assert(!cache->system->bypassCaches());
2278
2279 // functional snoop (note that in contrast to atomic we don't have
2280 // a specific functionalSnoop method, as they have the same
2281 // behaviour regardless)
2282 cache->functionalAccess(pkt, false);
2283}
2284
2285void
2286BaseCache::CacheReqPacketQueue::sendDeferredPacket()
2287{
2288 // sanity check
2289 assert(!waitingOnRetry);
2290
2291 // there should never be any deferred request packets in the
2292 // queue, instead we resly on the cache to provide the packets
2293 // from the MSHR queue or write queue
2294 assert(deferredPacketReadyTime() == MaxTick);
2295
2296 // check for request packets (requests & writebacks)
2297 QueueEntry* entry = cache.getNextQueueEntry();
2298
2299 if (!entry) {
2300 // can happen if e.g. we attempt a writeback and fail, but
2301 // before the retry, the writeback is eliminated because
2302 // we snoop another cache's ReadEx.
2303 } else {
2304 // let our snoop responses go first if there are responses to
2305 // the same addresses
2306 if (checkConflictingSnoop(entry->blkAddr)) {
2307 return;
2308 }
2309 waitingOnRetry = entry->sendPacket(cache);
2310 }
2311
2312 // if we succeeded and are not waiting for a retry, schedule the
2313 // next send considering when the next queue is ready, note that
2314 // snoop responses have their own packet queue and thus schedule
2315 // their own events
2316 if (!waitingOnRetry) {
2317 schedSendEvent(cache.nextQueueReadyTime());
2318 }
2319}
2320
2321BaseCache::MemSidePort::MemSidePort(const std::string &_name,
2322 BaseCache *_cache,
2323 const std::string &_label)
2324 : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2325 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2326 _snoopRespQueue(*_cache, *this, _label), cache(_cache)
2327{
2328}
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