base.cc (13745:1cf82fb6c4ab) | base.cc (13746:723109f11d56) |
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1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 351 unchanged lines hidden (view full) --- 360 doWritebacks(writebacks, forward_time); 361 } 362 363 // Here we charge the headerDelay that takes into account the latencies 364 // of the bus, if the packet comes from it. 365 // The latency charged is just the value set by the access() function. 366 // In case of a hit we are neglecting response latency. 367 // In case of a miss we are neglecting forward latency. | 1/* 2 * Copyright (c) 2012-2013, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 351 unchanged lines hidden (view full) --- 360 doWritebacks(writebacks, forward_time); 361 } 362 363 // Here we charge the headerDelay that takes into account the latencies 364 // of the bus, if the packet comes from it. 365 // The latency charged is just the value set by the access() function. 366 // In case of a hit we are neglecting response latency. 367 // In case of a miss we are neglecting forward latency. |
368 Tick request_time = clockEdge(lat) + pkt->headerDelay; | 368 Tick request_time = clockEdge(lat); |
369 // Here we reset the timing of the packet. 370 pkt->headerDelay = pkt->payloadDelay = 0; 371 372 if (satisfied) { 373 // notify before anything else as later handleTimingReqHit might turn 374 // the packet in a response 375 ppHit->notify(pkt); 376 --- 507 unchanged lines hidden (view full) --- 884} 885 886///////////////////////////////////////////////////// 887// 888// Access path: requests coming in from the CPU side 889// 890///////////////////////////////////////////////////// 891Cycles | 369 // Here we reset the timing of the packet. 370 pkt->headerDelay = pkt->payloadDelay = 0; 371 372 if (satisfied) { 373 // notify before anything else as later handleTimingReqHit might turn 374 // the packet in a response 375 ppHit->notify(pkt); 376 --- 507 unchanged lines hidden (view full) --- 884} 885 886///////////////////////////////////////////////////// 887// 888// Access path: requests coming in from the CPU side 889// 890///////////////////////////////////////////////////// 891Cycles |
892BaseCache::calculateAccessLatency(const CacheBlk* blk, | 892BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, |
893 const Cycles lookup_lat) const 894{ | 893 const Cycles lookup_lat) const 894{ |
895 Cycles lat(lookup_lat); | 895 Cycles lat(0); |
896 897 if (blk != nullptr) { | 896 897 if (blk != nullptr) { |
898 // First access tags, then data | 898 // As soon as the access arrives, for sequential accesses first access 899 // tags, then the data entry. In the case of parallel accesses the 900 // latency is dictated by the slowest of tag and data latencies. |
899 if (sequentialAccess) { | 901 if (sequentialAccess) { |
900 lat += dataLatency; 901 // Latency is dictated by the slowest of tag and data latencies | 902 lat = ticksToCycles(delay) + lookup_lat + dataLatency; |
902 } else { | 903 } else { |
903 lat = std::max(lookup_lat, dataLatency); | 904 lat = ticksToCycles(delay) + std::max(lookup_lat, dataLatency); |
904 } 905 906 // Check if the block to be accessed is available. If not, apply the 907 // access latency on top of when the block is ready to be accessed. | 905 } 906 907 // Check if the block to be accessed is available. If not, apply the 908 // access latency on top of when the block is ready to be accessed. |
909 const Tick tick = curTick() + delay; |
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908 const Tick when_ready = blk->getWhenReady(); | 910 const Tick when_ready = blk->getWhenReady(); |
909 if (when_ready > curTick() && 910 ticksToCycles(when_ready - curTick()) > lat) { 911 lat += ticksToCycles(when_ready - curTick()); | 911 if (when_ready > tick && 912 ticksToCycles(when_ready - tick) > lat) { 913 lat += ticksToCycles(when_ready - tick); |
912 } | 914 } |
915 } else { 916 // In case of a miss, apply lookup latency on top of the metadata 917 // delay, as the access can only start when it arrives. 918 lat = ticksToCycles(delay) + lookup_lat; |
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913 } 914 915 return lat; 916} 917 918bool 919BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 920 PacketList &writebacks) --- 4 unchanged lines hidden (view full) --- 925 chatty_assert(!(isReadOnly && pkt->isWrite()), 926 "Should never see a write in a read-only cache %s\n", 927 name()); 928 929 // Access block in the tags 930 Cycles tag_latency(0); 931 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency); 932 | 919 } 920 921 return lat; 922} 923 924bool 925BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 926 PacketList &writebacks) --- 4 unchanged lines hidden (view full) --- 931 chatty_assert(!(isReadOnly && pkt->isWrite()), 932 "Should never see a write in a read-only cache %s\n", 933 name()); 934 935 // Access block in the tags 936 Cycles tag_latency(0); 937 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency); 938 |
933 // Calculate access latency 934 lat = calculateAccessLatency(blk, tag_latency); | 939 // Calculate access latency on top of when the packet arrives. This 940 // takes into account the bus delay. 941 lat = calculateAccessLatency(blk, pkt->headerDelay, 942 tag_latency); |
935 936 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 937 blk ? "hit " + blk->print() : "miss"); 938 939 if (pkt->req->isCacheMaintenance()) { 940 // A cache maintenance operation is always forwarded to the 941 // memory below even if the block is found in dirty state. 942 --- 1508 unchanged lines hidden --- | 943 944 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 945 blk ? "hit " + blk->print() : "miss"); 946 947 if (pkt->req->isCacheMaintenance()) { 948 // A cache maintenance operation is always forwarded to the 949 // memory below even if the block is found in dirty state. 950 --- 1508 unchanged lines hidden --- |