1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64}
65
66BaseCache::BaseCache(const Params *p)
67 : MemObject(p),
68 mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
69 writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
70 MSHRQueue_WriteBuffer),
71 blkSize(p->block_size),
72 hitLatency(p->latency),
73 numTarget(p->tgts_per_mshr),
74 forwardSnoops(p->forward_snoops),
75 isTopLevel(p->is_top_level),
76 blocked(0),
77 noTargetMSHR(NULL),
78 missCount(p->max_miss_count),
79 drainEvent(NULL),
80 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),

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