1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43/**
44 * @file
45 * Definition of BaseCache functions.
46 */
47
48#include "cpu/base.hh"
49#include "cpu/smt.hh"
50#include "debug/Cache.hh"
51#include "mem/cache/base.hh"
52#include "mem/cache/mshr.hh"
53#include "sim/full_system.hh"
54
55using namespace std;
56
57BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
58 BaseCache *_cache,

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747{
748 int count = memSidePort->drain(de) + cpuSidePort->drain(de);
749
750 // Set status
751 if (count != 0) {
752 drainEvent = de;
753
754 changeState(SimObject::Draining);
755 return count;
756 }
757
758 changeState(SimObject::Drained);
759 return 0;
760}