1/*
2 * Copyright (c) 2012-2013, 2018-2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46 * Definition of BaseCache functions.
47 */
48
49#include "mem/cache/base.hh"
50
51#include "base/compiler.hh"
52#include "base/logging.hh"
53#include "debug/Cache.hh"
54#include "debug/CachePort.hh"
55#include "debug/CacheRepl.hh"
56#include "debug/CacheVerbose.hh"
57#include "mem/cache/compressors/base.hh"
58#include "mem/cache/mshr.hh"
59#include "mem/cache/prefetch/base.hh"
60#include "mem/cache/queue_entry.hh"
61#include "params/BaseCache.hh"
62#include "params/WriteAllocator.hh"
63#include "sim/core.hh"
64
65class BaseMasterPort;
66class BaseSlavePort;
67
68using namespace std;

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791 delete pkt;
792 }
793 }
794 }
795
796 return nullptr;
797}
798
799void
800BaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool)
801{
802 assert(pkt->isRequest());
803
804 assert(blk && blk->isValid());
805 // Occasionally this is not true... if we are a lower-level cache
806 // satisfying a string of Read and ReadEx requests from

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1031 // A writeback searches for the block, then writes the data.
1032 // As the block could not be found, it was a tag-only access.
1033 lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency);
1034
1035 return false;
1036 }
1037
1038 blk->status |= BlkReadable;
1039 } else {
1040 if (compressor) {
1041 // This is an overwrite to an existing block, therefore we need
1042 // to check for data expansion (i.e., block was compressed with
1043 // a smaller size, and now it doesn't fit the entry anymore).
1044 // If that is the case we might need to evict blocks.
1045 // @todo Update compression data
1046 }
1047 }
1048
1049 // only mark the block dirty if we got a writeback command,
1050 // and leave it as is for a clean writeback
1051 if (pkt->cmd == MemCmd::WritebackDirty) {
1052 // TODO: the coherent cache can assert(!blk->isDirty());
1053 blk->status |= BlkDirty;

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1120 lat = calculateTagOnlyLatency(pkt->headerDelay,
1121 tag_latency);
1122
1123 return false;
1124 }
1125
1126 blk->status |= BlkReadable;
1127 }
1128 } else {
1129 if (compressor) {
1130 // @todo Update compression data
1131 }
1132 }
1133
1134 // at this point either this is a writeback or a write-through
1135 // write clean operation and the block is already in this
1136 // cache, we need to update the data and the block flags
1137 assert(blk);
1138 // TODO: the coherent cache can assert(!blk->isDirty());

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1150 lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
1151
1152 // When the packet metadata arrives, the tag lookup will be done while
1153 // the payload is arriving. Then the block will be ready to access as
1154 // soon as the fill is done
1155 blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
1156 std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay));
1157
1158 // if this a write-through packet it will be sent to cache
1159 // below
1160 return !pkt->writeThrough();
1161 } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
1162 blk->isReadable())) {
1163 // OK to satisfy access
1164 incHitCount(pkt);
1165
1166 // Calculate access latency based on the need to access the data array
1167 if (pkt->isRead() || pkt->isWrite()) {

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2360 for (int i = 0; i < system->maxMasters(); i++) {
2361 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
2362 }
2363
2364 replacements
2365 .name(name() + ".replacements")
2366 .desc("number of replacements")
2367 ;
2368}
2369
2370void
2371BaseCache::regProbePoints()
2372{
2373 ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit");
2374 ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss");
2375 ppFill = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Fill");

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