1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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885}
886
887/////////////////////////////////////////////////////
888//
889// Access path: requests coming in from the CPU side
890//
891/////////////////////////////////////////////////////
892Cycles
893BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
894 const Cycles lookup_lat) const
895{
896 Cycles lat(0);
897
898 if (blk != nullptr) {
899 // As soon as the access arrives, for sequential accesses first access
900 // tags, then the data entry. In the case of parallel accesses the

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909 // access latency on top of when the block is ready to be accessed.
910 const Tick tick = curTick() + delay;
911 const Tick when_ready = blk->getWhenReady();
912 if (when_ready > tick &&
913 ticksToCycles(when_ready - tick) > lat) {
914 lat += ticksToCycles(when_ready - tick);
915 }
916 } else {
917 // In case of a miss, apply lookup latency on top of the metadata
918 // delay, as the access can only start when it arrives.
919 lat = ticksToCycles(delay) + lookup_lat;
920 }
921
922 return lat;
923}
924
925bool
926BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
927 PacketList &writebacks)

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932 chatty_assert(!(isReadOnly && pkt->isWrite()),
933 "Should never see a write in a read-only cache %s\n",
934 name());
935
936 // Access block in the tags
937 Cycles tag_latency(0);
938 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency);
939
940 // Calculate access latency on top of when the packet arrives. This
941 // takes into account the bus delay.
942 lat = calculateAccessLatency(blk, pkt->headerDelay,
943 tag_latency);
944
945 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
946 blk ? "hit " + blk->print() : "miss");
947
948 if (pkt->req->isCacheMaintenance()) {
949 // A cache maintenance operation is always forwarded to the
950 // memory below even if the block is found in dirty state.
951
952 // We defer any changes to the state of the block until we
953 // create and mark as in service the mshr for the downstream
954 // packet.
955 return false;
956 }
957
958 if (pkt->isEviction()) {
959 // We check for presence of block in above caches before issuing
960 // Writeback or CleanEvict to write buffer. Therefore the only
961 // possible cases can be of a CleanEvict packet coming from above
962 // encountering a Writeback generated in this cache peer cache and

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976 // peer caches of the same level while traversing the
977 // crossbar. If a copy of the block is found, the
978 // packet is deleted in the crossbar. Hence, none of
979 // the other upper level caches connected to this
980 // cache have the block, so we can clear the
981 // BLOCK_CACHED flag in the Writeback if set and
982 // discard the CleanEvict by returning true.
983 wbPkt->clearBlockCached();
984 return true;
985 } else {
986 assert(pkt->cmd == MemCmd::WritebackDirty);
987 // Dirty writeback from above trumps our clean
988 // writeback... discard here
989 // Note: markInService will remove entry from writeback buffer.
990 markInService(wb_entry);
991 delete wbPkt;

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1001 // we could get a clean writeback while we are having
1002 // outstanding accesses to a block, do the simple thing for
1003 // now and drop the clean writeback so that we do not upset
1004 // any ordering/decisions about ownership already taken
1005 if (pkt->cmd == MemCmd::WritebackClean &&
1006 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
1007 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
1008 "dropping\n", pkt->getAddr());
1009 return true;
1010 }
1011
1012 if (!blk) {
1013 // need to do a replacement
1014 blk = allocateBlock(pkt, writebacks);
1015 if (!blk) {
1016 // no replaceable block available: give up, fwd to next level.
1017 incMissCount(pkt);
1018 return false;
1019 }
1020
1021 blk->status |= BlkReadable;
1022 }
1023 // only mark the block dirty if we got a writeback command,
1024 // and leave it as is for a clean writeback
1025 if (pkt->cmd == MemCmd::WritebackDirty) {

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1038 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1039 incHitCount(pkt);
1040
1041 // When the packet metadata arrives, the tag lookup will be done while
1042 // the payload is arriving. Then the block will be ready to access as
1043 // soon as the fill is done
1044 blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
1045 std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay));
1046 return true;
1047 } else if (pkt->cmd == MemCmd::CleanEvict) {
1048 if (blk) {
1049 // Found the block in the tags, need to stop CleanEvict from
1050 // propagating further down the hierarchy. Returning true will
1051 // treat the CleanEvict like a satisfied write request and delete
1052 // it.
1053 return true;
1054 }
1055 // We didn't find the block here, propagate the CleanEvict further

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1061 // WriteClean handling is a special case. We can allocate a
1062 // block directly if it doesn't exist and we can update the
1063 // block immediately. The WriteClean transfers the ownership
1064 // of the block as well.
1065 assert(blkSize == pkt->getSize());
1066
1067 if (!blk) {
1068 if (pkt->writeThrough()) {
1069 // if this is a write through packet, we don't try to
1070 // allocate if the block is not present
1071 return false;
1072 } else {
1073 // a writeback that misses needs to allocate a new block
1074 blk = allocateBlock(pkt, writebacks);
1075 if (!blk) {
1076 // no replaceable block available: give up, fwd to
1077 // next level.
1078 incMissCount(pkt);
1079 return false;
1080 }
1081
1082 blk->status |= BlkReadable;
1083 }
1084 }
1085
1086 // at this point either this is a writeback or a write-through

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1099 incHitCount(pkt);
1100
1101 // When the packet metadata arrives, the tag lookup will be done while
1102 // the payload is arriving. Then the block will be ready to access as
1103 // soon as the fill is done
1104 blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
1105 std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay));
1106
1107 // if this a write-through packet it will be sent to cache
1108 // below
1109 return !pkt->writeThrough();
1110 } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
1111 blk->isReadable())) {
1112 // OK to satisfy access
1113 incHitCount(pkt);
1114 satisfyRequest(pkt, blk);
1115 maintainClusivity(pkt->fromCache(), blk);
1116
1117 return true;
1118 }
1119
1120 // Can't satisfy access normally... either no block (blk == nullptr)
1121 // or have block but need writable
1122
1123 incMissCount(pkt);
1124
1125 if (!blk && pkt->isLLSC() && pkt->isWrite()) {
1126 // complete miss on store conditional... just give up now
1127 pkt->req->setExtraData(0);
1128 return true;
1129 }
1130
1131 return false;
1132}

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