1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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360 doWritebacks(writebacks, forward_time);
361 }
362
363 // Here we charge the headerDelay that takes into account the latencies
364 // of the bus, if the packet comes from it.
365 // The latency charged is just the value set by the access() function.
366 // In case of a hit we are neglecting response latency.
367 // In case of a miss we are neglecting forward latency.
368 Tick request_time = clockEdge(lat) + pkt->headerDelay;
369 // Here we reset the timing of the packet.
370 pkt->headerDelay = pkt->payloadDelay = 0;
371
372 if (satisfied) {
373 // notify before anything else as later handleTimingReqHit might turn
374 // the packet in a response
375 ppHit->notify(pkt);
376

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884}
885
886/////////////////////////////////////////////////////
887//
888// Access path: requests coming in from the CPU side
889//
890/////////////////////////////////////////////////////
891Cycles
892BaseCache::calculateAccessLatency(const CacheBlk* blk,
893 const Cycles lookup_lat) const
894{
895 Cycles lat(lookup_lat);
896
897 if (blk != nullptr) {
898 // First access tags, then data
899 if (sequentialAccess) {
900 lat += dataLatency;
901 // Latency is dictated by the slowest of tag and data latencies
902 } else {
903 lat = std::max(lookup_lat, dataLatency);
904 }
905
906 // Check if the block to be accessed is available. If not, apply the
907 // access latency on top of when the block is ready to be accessed.
908 const Tick when_ready = blk->getWhenReady();
909 if (when_ready > curTick() &&
910 ticksToCycles(when_ready - curTick()) > lat) {
911 lat += ticksToCycles(when_ready - curTick());
912 }
913 }
914
915 return lat;
916}
917
918bool
919BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
920 PacketList &writebacks)

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925 chatty_assert(!(isReadOnly && pkt->isWrite()),
926 "Should never see a write in a read-only cache %s\n",
927 name());
928
929 // Access block in the tags
930 Cycles tag_latency(0);
931 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency);
932
933 // Calculate access latency
934 lat = calculateAccessLatency(blk, tag_latency);
935
936 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
937 blk ? "hit " + blk->print() : "miss");
938
939 if (pkt->req->isCacheMaintenance()) {
940 // A cache maintenance operation is always forwarded to the
941 // memory below even if the block is found in dirty state.
942

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