1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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473 if (is_fill && !is_error) {
474 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
475 pkt->getAddr());
476
477 const bool allocate = (writeAllocator && mshr->wasWholeLineWrite) ?
478 writeAllocator->allocate() : mshr->allocOnFill();
479 blk = handleFill(pkt, blk, writebacks, allocate);
480 assert(blk != nullptr);
481 }
482
483 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) {
484 // The block was marked not readable while there was a pending
485 // cache maintenance operation, restore its flag.
486 blk->status |= BlkReadable;
487
488 // This was a cache clean operation (without invalidate)

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2218 ;
2219}
2220
2221void
2222BaseCache::regProbePoints()
2223{
2224 ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit");
2225 ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss");
2226}
2227
2228///////////////
2229//
2230// CpuSidePort
2231//
2232///////////////
2233bool

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