1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47 */
48
49#include "mem/cache/base.hh"
50
51#include "base/compiler.hh"
52#include "base/logging.hh"
53#include "debug/Cache.hh"
54#include "debug/CachePort.hh"
55#include "debug/CacheVerbose.hh"
56#include "mem/cache/mshr.hh"
57#include "mem/cache/prefetch/base.hh"
58#include "mem/cache/queue_entry.hh"
59#include "params/BaseCache.hh"
60#include "sim/core.hh"
61
62class BaseMasterPort;

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1232 // Find replacement victim
1233 std::vector<CacheBlk*> evict_blks;
1234 CacheBlk *victim = tags->findVictim(addr, is_secure, evict_blks);
1235
1236 // It is valid to return nullptr if there is no victim
1237 if (!victim)
1238 return nullptr;
1239
1240 // Check for transient state allocations. If any of the entries listed
1241 // for eviction has a transient state, the allocation fails
1242 for (const auto& blk : evict_blks) {
1243 if (blk->isValid()) {
1244 Addr repl_addr = regenerateBlkAddr(blk);
1245 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
1246 if (repl_mshr) {
1247 // must be an outstanding upgrade or clean request

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