1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1321
1322 return pkt;
1323}
1324
1325
1326void
1327BaseCache::memWriteback()
1328{
1329 CacheBlkVisitorWrapper visitor(*this, &BaseCache::writebackVisitor);
1330 tags->forEachBlk(visitor);
1331}
1332
1333void
1334BaseCache::memInvalidate()
1335{
1336 CacheBlkVisitorWrapper visitor(*this, &BaseCache::invalidateVisitor);
1337 tags->forEachBlk(visitor);
1338}
1339
1340bool
1341BaseCache::isDirty() const
1342{
1343 CacheBlkIsDirtyVisitor visitor;
1344 tags->forEachBlk(visitor);
1345
1346 return visitor.isDirty();
1347}
1348
1349bool
1350BaseCache::writebackVisitor(CacheBlk &blk)
1351{
1352 if (blk.isDirty()) {
1353 assert(blk.isValid());
1354
1355 Request request(tags->regenerateBlkAddr(&blk),
1356 blkSize, 0, Request::funcMasterId);
1357 request.taskId(blk.task_id);
1358 if (blk.isSecure()) {
1359 request.setFlags(Request::SECURE);
1360 }
1361
1362 Packet packet(&request, MemCmd::WriteReq);
1363 packet.dataStatic(blk.data);
1364
1365 memSidePort.sendFunctional(&packet);
1366
1367 blk.status &= ~BlkDirty;
1368 }
1369
1370 return true;
1371}
1372
1373bool
1374BaseCache::invalidateVisitor(CacheBlk &blk)
1375{
1376 if (blk.isDirty())
1377 warn_once("Invalidating dirty cache lines. " \
1378 "Expect things to break.\n");
1379
1380 if (blk.isValid()) {
1381 assert(!blk.isDirty());
1382 invalidateBlock(&blk);
1383 }
1384
1385 return true;
1386}
1387
1388Tick
1389BaseCache::nextQueueReadyTime() const
1390{
1391 Tick nextReady = std::min(mshrQueue.nextReadyTime(),
1392 writeBuffer.nextReadyTime());
1393

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